AM3517_14 Datasheet, PDF (104/223 Pages) Texas Instruments – ARM Microprocessors

AM3517, AM3505
SPRS550E – OCTOBER 2009 – REVISED MARCH 2013
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5.3 Analog Supply (vdda_dac) Noise Requirements
In order to assure 10-bit accuracy of the DAC analog output, the analog supply vdda_dac has to meet the
noise requirements stated in this section.
The DAC Power Supply Rejection Ratio is defined as the relative variation of the full-scale output current
divided by the supply variation. Thus, it is expressed in percentage of Full-Scale Range (FSR) per volt of
100 × ^DIOUT
I
PSRR
DAC
=
supply variation as shown in the following equation:
OUTFS
V
AC
% FSR
V
Depending on frequency, the PSRR is defined in Table 5-4.
Table 5-4. Video DAC Power Supply Rejection Ratio
Supply Noise Frequency
0 to 100 kHz
> 100 kHz
PSRR % FSR/V
1
The rejection decreases 20 dB/dec.
Example: at 1 MHz the PSRR is 10% of FSR/V
A graphic representation is shown in Figure 5-2.
PSRR (% FSR/V)
First pole of
DAC output load
10
1
100 kHz 1 MHz
f
030-019
Figure 5-2. Video DAC Power Supply Rejection Ratio
To ensure that the DAC SFDR specification is met, the PSRR values and the clock jitter requirements
translate to the following limits on vdda_dac (for the Video DAC).
The maximum peak-to-peak noise on vdda (ripple) is defined in Table 5-5:
Table 5-5. Video DAC Maximum Peak-to-Peak Noise on vdda_dac
Tone Frequency
0 to 100 kHz
> 100 kHz
Maximum Peak-to-Peak Noise on vdda_dac
< 30 mVpp
Decreases 20 dB/dec.
Example: at 1 MHz the maximum is 3 mVpp
The maximum noise spectral density (white noise) is defined in Table 5-6:
Table 5-6. Video DAC Maximum Noise Spectral Density
Supply Noise Bandwidth
0 to 100 kHz
> 100 kHz
Maximum Supply Noise Density
< 20 V / Hz
Decreases 20 dB/dec.
Example: at 1 MHz the maximum noise density is 2 / Hz
104 Video DAC Specifications
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