AM3517_14 Datasheet, PDF (108/223 Pages) Texas Instruments – ARM Microprocessors

AM3517, AM3505
SPRS550E – OCTOBER 2009 – REVISED MARCH 2013
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6.4 External Memory Interfaces
The AM3517/05 processor includes the following external memory interfaces:
• General-purpose memory controller (GPMC)
• SDRAM controller (SDRC)
6.4.1 General-Purpose Memory Controller (GPMC)
The GPMC is the AM3517/05 unified memory controller used to interface external memory devices such
as:
• Asynchronous SRAM-like memories and ASIC devices
• Asynchronous page mode and synchronous burst NOR flash
• NAND flash
6.4.1.1 GPMC/NOR Flash Interface Synchronous Timing
The following tables assume testing over the recommended operating conditions and electrical
characteristic conditions.
Table 6-2. GPMC/NOR Flash Synchronous Mode Timing Conditions
TIMING CONDITION PARAMETER
Input Conditions
t_R
t_F
Output Conditions
C_LOAD
Input signal rise time
Input signal fall time
Output load capacitance
1.8V, 3.3V
MIN
MAX
0.3
1.8
0.3
1.8
30
UNIT
ns
ns
pF
Table 6-3. GPMC/NOR Flash Interface Timing Requirements Synchronous Mode
NO.
PARAMETER
F12
t_su(DV-CLKH)
Setup time, read gpmc_d[15:0] valid before
gpmc_clk high
F13
F21
F22
t_h(CLKH-DV)
t_{su(WAITV-CLKH)}
t_{h(CLKH-WAITV)}
Hold time, gpmc_d[15:0] valid after gpmc_clk high
Setup time, gpmc_waitx⁽¹⁾ valid before gpmc_clk
high
Hold Time, gpmc_waitx⁽¹⁾ valid after gpmc_clk
high
(1) Wait monitoring support is limited to a WaitMonitoringTime value > 0.
1.8V, 3.3V
MIN
MAX
2.021
3.403
3.782
3.343
UNIT
ns
ns
ns
ns
108 Timing Requirements and Switching Characteristics
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