AM3517_14 Datasheet, PDF (103/223 Pages) Texas Instruments – ARM Microprocessors

AM3517, AM3505
www.ti.com
SPRS550E – OCTOBER 2009 – REVISED MARCH 2013
(T_MIN to T_MAX, vdda_dac = 1.8 V, R_OUT1/2 = 1650 , R_LOAD = 75 , unless otherwise noted)
Table 5-3. Video DAC Dynamic Electrical Specification
f_CLK ⁽¹⁾
PARAMETER
Output update rate
Clock jitter
CONDITIONS/ASSUMPTIONS
MIN
TYP
MAX
UNIT
Equal to input clock frequency
54
MHz
rms clock jitter required in order to assure 10-
bit accuracy
40
ps
Attenuation at 5.1 MHz
Attenuation at 54 MHz⁽¹⁾
Corner frequency for signal
Image frequency
0.1
0.5
1.5
dB
25
30
33
dB
t_ST
Output settling time
Time from the start of the output transition to
85
ns
output within 1 LSB of final value.
t_Rout
Output rise time
Measured from 10% to 90% of full-scale
transition
25
ns
t_Fout
Output fall time
Measured from 10% to 90% of full-scale
transition
25
ns
BW
Signal bandwidth
Differential gain⁽²⁾
Differential phase⁽²⁾
6
1.5%
1
MHz
deg.
SFDR
SNR
PSRR
Within bandwidth
Signal-to-noise ratio
1 kHz to 6 MHz bandwidth
Power supply rejection ratio
f_CLK = 54 MHz, f_OUT = 1 MHz
f_CLK = 54 MHz, f_OUT = 1 MHz
Up to 6 MHz
45
dB
55 ⁽³⁾
dB
20 ⁽⁴⁾
dB
Crosstalk Between the two video
channels
50
40
dB
(1) For internal input clock information, For more information, see the Device Display Interface Subsystem Reference Guide [literature
number SPRUFV2].
(2) The differential gain and phase value is for dc coupling. Note that there is degradation for the ac coupling.
(3) The SNR value is for dc coupling. Note that there is a 6-dB degradation for ac coupling.
(4) The PSSR value is for dc coupling. Note that there is a 10-dB degradation for ac coupling.
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Video DAC Specifications 103