CC1350_16 Datasheet, PDF (10/61 Pages) Texas Instruments – SimpleLink Ultra-Low-Power Dual-Band Wireless MCU

CC1350
SWRS183A – JUNE 2016 – REVISED NOVEMBER 2016
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4.4 Signal Descriptions – RHB Package
Table 4-2. Signal Descriptions – RHB Package
PIN
NAME
NO.
DCDC_SW
17
DCOUPL
12
TYPE
Power
Power
DESCRIPTION
Output from internal DC-DC⁽¹⁾
1.27-V regulated digital-supply decoupling⁽²⁾
DIO_0
6
Digital I/O
GPIO, Sensor Controller
DIO_1
7
Digital I/O
GPIO, Sensor Controller
DIO_2
8
Digital I/O
GPIO, Sensor Controller, high-drive capability
DIO_3
9
Digital I/O
GPIO, Sensor Controller, high-drive capability
DIO_4
10
Digital I/O
GPIO, Sensor Controller, high-drive capability
DIO_5
15
Digital I/O
GPIO, high-drive capability, JTAG_TDO
DIO_6
16
Digital I/O
GPIO, high-drive capability, JTAG_TDI
DIO_7
20
Digital or analog I/O GPIO, Sensor Controller, analog
DIO_8
21
Digital or analog I/O GPIO, Sensor Controller, analog
DIO_9
22
Digital or analog I/O GPIO, Sensor Controller, analog
DIO_10
23
Digital or analog I/O GPIO, Sensor Controller, Analog
DIO_11
24
Digital or analog I/O GPIO, Sensor Controller, analog
DIO_12
25
Digital or analog I/O GPIO, Sensor Controller, analog
DIO_13
26
Digital or analog I/O GPIO, Sensor Controller, analog
DIO_14
27
Digital or analog I/O GPIO, Sensor Controller, analog
EGP
–
Power
Ground; exposed ground pad
JTAG_TMSC
13
Digital I/O
JTAG TMSC, high-drive capability
JTAG_TCKC
14
Digital I/O
JTAG TCKC
RESET_N
19
Digital input
Reset, active low. No internal pullup.
RF_N
2
RF I/O
Negative RF input signal to LNA during RX
Negative RF output signal from PA during TX
RF_P
1
RF I/O
Positive RF input signal to LNA during RX
Positive RF output signal from PA during TX
RX_TX
3
VDDR
29
VDDR_RF
32
VDDS
28
VDDS2
11
RF I/O
Power
Power
Power
Power
Optional bias pin for the RF LNA
1.7-V to 1.95-V supply, connect to output of internal DC-DC ⁽²⁾⁽³⁾
1.7-V to 1.95-V supply, connect to output of internal DC-DC ⁽²⁾⁽⁴⁾
1.8-V to 3.8-V main chip supply⁽¹⁾
1.8-V to 3.8-V GPIO supply⁽¹⁾
VDDS_DCDC
18
Power
1.8-V to 3.8-V DC-DC supply
X24M_N
30
Analog I/O
24-MHz crystal oscillator pin 1
X24M_P
31
Analog I/O
24-MHz crystal oscillator pin 2
X32K_Q1
4
Analog I/O
32-kHz crystal oscillator pin 1
X32K_Q2
5
Analog I/O
32-kHz crystal oscillator pin 2
(1) For more details, see the technical reference manual listed in Section 8.3.
(2) Do not supply external circuitry from this pin.
(3) If internal DC-DC is not used, this pin is supplied internally from the main LDO.
(4) If internal DC-DC is not used, this pin must be connected to VDDR for supply from the main LDO.
10
Terminal Configuration and Functions
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