TMS320DM6467_08 Datasheet, PDF (98/340 Pages) Texas Instruments – Digital Media System-on-Chip

TMS320DM6467
Digital Media System-on-Chip
SPRS403A – DECEMBER 2007 – REVISED MAY 2008
www.ti.com
3.4.2.4 ARMBOOT Register
The ARM Boot Configuration (ARMBOOT) register is used to control the ARM926 boot. The ARMBOOT
value does not change as a result of a soft reset, instead the last value written is retained.
When ROM boot is selected (BTMODE[3:0] ≠ 0100), a jump to the internal TCM ROM (0x0000 8000) is
forced into the first fetched instruction word. The embedded ROM boot loader (RBL) code can then
perform certain configuration steps, read the BOOTCFG register to determine the desired boot method,
and branch to an appropriate secondary loader utility.
If EMIFA boot is selected (BTMODE[3:0] = 0100), a jump to the highest branch address (0x0200 0000) is
forced into the first fetched instruction word. This must be modified to address 0x4200 0000 in order to
map to the EMIFA. The ARM will then continue executing from external memory using the default EMIFA
timings until modified by software. Note: that either NOR Flash or ROM must be connected to the first
EMIFA chip select space (EM_CS2). The EMIFA does not support direct execution from NAND Flash.
31
RESERVED
5
4
3
1
0
ADDRMOD
RESERVED
TRAMBOOT
R-0000 0000 0000 0000 0000 0000 000
LEGEND: R/W = Read/Write; R = Read only; C = Clear; -n = value after reset
R/W-C
R-000
R/W-0
Figure 3-9. ARMBOOT Register
Table 3-11. ARMBOOT Register Bit Descriptions
BIT
NAME
DESCRIPTION
31:5
RESERVED Reserved. Read returns "0".
IAHB Address Modification.
0 = No address modification.
1 = Address bit 30 is tied high to modify IAHB fetch address to point to EMIFA.
The default value for this bit is determined by the BOOTMODE configuration bits (BTMODE[3:0]). If
BTMODE[3:0] = 0100 [EMIFA direct boot (ROM/NOR)] , then ADDRMOD defaults to "1" so that
4
ADDRMOD instruction fetches from the ARM will point to EMIFA CS2 memory space. For all other
BTMODE[3:0] values, ADDRMOD defaults to "0" because ARM will boot from its TCM (ROM or
RAM).
The ADDRMOD value is ignored when TRAMBOOT is set (1) [address modification is disabled].
After branching into the EMIFA CS2 space, software should clear this bit as part of the reset routine
so that subsequent IAHB access addresses are not modified.
3:1
RESERVED Reserved. Read returns "0".
ARM TCM RAM Boot.
0 = Use BTMODE[3:0] selected boot mode
1 = Boot from ITCM RAM
0
TRAMBOOT This is a "sticky" bit that can be used to force the ARM926 to boot from ITCM RAM. On POR reset,
this bit will be initialized to "0" because TCM RAM is not initialized; otherwise, the bit retains the
value. After initializing ITCM RAM, software can set this bit so that subsequent Warm Reset
(RESET) or Soft Reset will boot from the ITCM.
3.4.2.5 ARMWAIT Register
The ARM Wait State Control (ARMWAIT) register is used to control ARM926 accesses to its TCM RAM.
At normal ARM operating frequency, a wait state must be inserted when accessing TCM RAM. When the
device is operated at low speeds, performance may be increased by removing the wait state. Note: TCM
ROM will always operate with a wait state enabled.
31
RESERVED
1
0
RAMWAIT
R-0000 0000 0000 0000 0000 0000 0000 000
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
R/W-1
Figure 3-10. ARMWAIT Register
98
Device Configurations
Submit Documentation Feedback