TMS320DM6467_08 Datasheet, PDF (70/340 Pages) Texas Instruments – Digital Media System-on-Chip

TMS320DM6467
Digital Media System-on-Chip
SPRS403A – DECEMBER 2007 – REVISED MAY 2008
www.ti.com
Table 2-29. General Purpose Input/Output (GPIO) Terminal Functions (continued)
SIGNAL
NAME
DIOW/
GP[20]/
EM_WAIT4
IORDY/
GP[21]/
EM_WAIT3
USB_DRVVBUS/
GP[22]
URXD1/
TS0_DIN7/
GP[23]
UTXD1/
URCTX1/
TS0_DOUT7/
GP[24]
URTS1/
UIRTX1/
TS0_WAITO/
GP[25]
UCTS1/USD1/
TS0_EN_WAITO/
GP[26]
GP[27:31]
PCI_CBE1/
ATA_CS1/
GP[32]/
EM_A[19]
PCI_CBE0/
ATA_CS0/
GP[33]/
EM_A[18]
GP[34:35]
UDTR0/
TS0_ENAO/
GP[36]
UDSR0/
TS0_PSTO/
GP[37]
UDCD0/
TS0_WAITIN/
GP[38]
URXD2/
CRG1_VCXI/
GP[39]/
CRG0_VCXI
UTXD2/URCTX2/
CRG1_PO/
GP[40]/
CRG0_PO
NO.
A11
D11
B18
Y18
AB19
AA18
Y17
n/a
C2
F4
n/a
Y12
AB11
AA11
AB20
AA19
TYPE ⁽¹⁾
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
–
I/O/Z
I/O/Z
–
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
URTS2/UIRTX2/
TS0_PSTIN/ AC20
GP[41]
I/O/Z
UCTS2/USD2/
CRG0_VCXI/
GP[42]/
TS1_PSTO
GP[43:47]
AC21
n/a
I/O/Z
–
OTHER ^{(2) (3)}
IPU
DV_DD33
IPU
DV_DD33
IPD
DV_DD33
IPD
DV_DD33
IPD
DV_DD33
IPD
DV_DD33
IPU
DV_DD33
–
IPU
DV_DD33
IPU
DV_DD33
–
IPU
DV_DD33
IPU
DV_DD33
IPU
DV_DD33
IPD
DV_DD33
IPD
DV_DD33
IPU
DV_DD33
IPU
DV_DD33
–
DESCRIPTION
These pins are multiplexed between ATA, GPIO, and EMIFA.
When 32-bit HPI mode is enabled (PINMUX0.PCIEN = 0, PINMUX0.HPIEN = 1,
PINMUX0.ATAEN = 0), these pins are GP[20:21] (I/0/Z).
This pin is multiplexed between USB and GPIO.
When not used for USB (PINMUX0.VBUSDIS = 1), this pin is GP[22] (I/O/Z).
This pin is multiplexed between UART1, TSIF0, and GPIO.
When UART1 GPIO muxing is selected (PINMUX1.UART1CTL = 11) and TSIF0
serial input is not enabled (PINMUX0.PTSIMUX ≠ 11), this pin is GP[23] (I/O/Z).
This pin is multiplexed between UART1, TSIF0, and GPIO.
When UART1 GPIO muxing is selected (PINMUX1. UART1CTL = 11) and TSIF0
serial input is not enabled (PINMUX0.PTSIMUX ≠ 11), this pin is GP[24] (I/O/Z).
These pins are multiplexed between UART1, TSIF0, and GPIO.
When UART1 GPIO muxing is selected (PINMUX1.UART1CTL = 11) and TSIF0
input is not enabled (PINMUX0.PTSIMUX = 0x), these pins are GP[25:26] (I/O/Z).
GP[27:31] are not pinned out on this device.
These pins are multiplexed between PCI, ATA, GPIO, and EMIFA.
When 32-bit HPI mode is enabled (PINMUX0.PCIEN = 0, PINMUX0.HPIEN = 1,
PINMUX0.ATAEN = 0), these pins are GP[32:33] (I/O/Z).
GP[34:35] are not pinned out on this device.
These pins are multiplexed between UART0, TSIF0, and GPIO.
When UART0 UART with modem functional muxing is not selected
(PINMUX1.UART0CTL ≠ 00) and TSIF0 output muxing is not enabled
(PINMUX0.PTSOMUX ≠ 1x), these pins are GP[36:38] (I/O/Z).
These pins are multiplexed between UART2, CRGEN1, GPIO, and CRGEN0.
When UART2 UART GPIO muxing is selected (PINMUX1.UART2CTL = 11) and
CRGEN0/1 are not enabled (PINMUX0.CRGMUX ≠ x01, 110), these pins are
GP[39:40] (I/O/Z).
This pin is multiplexed between UART2, TSIF0, and GPIO.
When UART2 UART without flow control or GPIO muxing is selected
(PINMUX1.UART2CTL = x1) and TSIF0 input is not enabled
(PINMUX0.PTSIMUX = 0x), this pin is GP[41] (I/O/Z).
This pin is multiplexed between UART2, CRGEN0, GPIO, and TSIF1.
When UART2 UART without flow control or GPIO muxing is selected
(PINMUX1.UART2CTL = x1) and CRGEN0 on UART2/PWM muxing is not enabled
(PINMUX0.CRGMUX ≠ 10x) and TSIF1 output is not enabled
(PINMUX0.TSSOMUX = 0x), this pin is GP[42] (I/O/Z).
GP[43:47] are not pinned out on this device.
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