TMS320DM6467_08 Datasheet, PDF (42/340 Pages) Texas Instruments – Digital Media System-on-Chip

TMS320DM6467
Digital Media System-on-Chip
SPRS403A – DECEMBER 2007 – REVISED MAY 2008
www.ti.com
Table 2-10. DDR2 Memory Controller Terminal Functions (continued)
SIGNAL
NAME
DDR_D[31]
DDR_D[30]
DDR_D[29]
DDR_D[28]
DDR_D[27]
DDR_D[26]
DDR_D[25]
DDR_D[24]
DDR_D[23]
DDR_D[22]
DDR_D[21]
DDR_D[20]
DDR_D[19]
DDR_D[18]
DDR_D[17]
DDR_D[16]
DDR_D[15]
DDR_D[14]
DDR_D[13]
DDR_D[12]
DDR_D[11]
DDR_D[10]
DDR_D[9]
DDR_D[8]
DDR_D[7]
DDR_D[6]
DDR_D[5]
DDR_D[4]
DDR_D[3]
DDR_D[2]
DDR_D[1]
DDR_D[0]
DDR_DQGATE0
DDR_DQGATE1
DDR_DQGATE2
DDR_DQGATE3
DDR_VREF
DDR_ZP
DDR_ZN
NO.
Y20
W20
Y21
AA21
U21
T21
R20
T20
AB22
Y22
AA22
AA23
V23
U23
T22
U22
H22
G23
G22
F23
E23
C22
B22
C23
H20
G21
F21
G20
B21
C20
D20
C21
J19
J21
R19
R21
P23
TYPE ⁽¹⁾
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I
L19 O/Z
M19 O/Z
OTHER ^{(2) (3)}
DV_DDR2
DV_DDR2
DV_DDR2
DV_DDR2
DV_DDR2
(3)
(3)
(3)
DESCRIPTION
DDR2 data bus can be configured as 32 bits wide or 16 bits wide.
DDR2 strobe gate signal for lower-half data bus
DDR2 strobe gate signal return for lower-half data bus
DDR2 strobe gate signal for upper-half data bus
DDR2 strobe gate signal return for upper-half data bus
Reference voltage input for the SSTL_18 IO buffers.
Impedance control for DDR2 outputs. This must be connected via a 48.7-Ω (±0.5%
tolerance) resistor to V_SS.
Impedance control for DDR2 outputs. This must be connected via a 48.7-Ω (±0.5%
tolerance) resistor to DV_DDR2.
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