TMS320DM6467_08 Datasheet, PDF(253/340 Page) Texas Instruments – Digital Media System-on-Chip

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TMS320DM6467_08 Datasheet, PDF (253/340 Pages) Texas Instruments – Digital Media System-on-Chip

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TMS320DM6467

Digital Media System-on-Chip

SPRS403A â DECEMBER 2007 â REVISED MAY 2008

Table 6-70. HPI Master Memory Map (continued)

START ADDRESS

0x1002 0000

0x1100 0000

0x1140 0000

0x1150 0000

0x1160 0000

0x1170 0000

0x1180 0000

0x1181 0000

0x1181 8000

0x1183 8000

0x1190 0000

0x11E0 0000

0x11E0 8000

0x11F0 0000

0x11F0 8000

0x1200 0000

0x4C00 0000

0x5000 0000

0x8000 0000

0x9000 0000

0xA000 0000

0xC000 0000

END ADDRESS

0x10FF FFFF

0x113F FFFF

0x114F FFFF

0x115F FFFF

0x116F FFFF

0x117F FFFF

0x1180 FFFF

0x1181 7FFF

0x1183 7FFF

0x118F FFFF

0x11DF FFFF

0x11E0 7FFF

0x11EF FFFF

0x11F0 7FFF

0x11FF FFFF

0x4BFF FFFF

0x4FFF FFFF

0x7FFF FFFF

0x8FFF FFFF

0x9FFF FFFF

0xBFFF FFFF

0xFFFF FFFF

SIZE

(BYTES)

16256K

4M

1M

1M

1M

1M

64K

32K

128K

800K

5M

32K

992K

32K

992K

928M

64M

768M

256M

256M

512M

1G

HPI ACCESS

Reserved

C64x+ L2 RAM/Cache

Reserved

C64x+ L1P RAM/Cache

Reserved

C64x+ L1D RAM/Cache

Reserved

VLYNQ (Remote Data)

Reserved

DDR2 Memory Controller

Reserved

Reserved

Reserved

6.17.3 HPI Peripheral Register Description(s)

Table 6-71. HPI Control Registers

HEX ADDRESS RANGE

01C6 7800

01C6 7804

01C6 7808 - 01C6 782F

01C6 7830

01C6 7834

01C6 7838

01C6 783C - 01C6 7FFF

ACRONYM

PID

PWREMU_MGMT

-

HPIC

HPIA

(HPIAW) (1)

HPIA

(HPIAR) (1)

-

REGISTER NAME

Peripheral Identification Register

HPI power and emulation management register

Reserved

HPI control register

HPI address register

(Write)

HPI address register

(Read)

Reserved

COMMENTS

The ARM/C64x+ has

read/write access to the

PWREMU_MGMT register.

The Host and the

ARM/C64x+ both have

read/write access to the

HPIC register.

The Host has read/write

access to the HPIA registers.

The ARM/C64x+ has only

read access to the HPIA

registers.

(1) There are two 32-bit HPIA registers: HPIAR for read operations and HPIAW for write operations. The HPI can be configured such that

HPIAR and HPIAW act as a single 32-bit HPIA (single-HPIA mode) or as two separate 32-bit HPIAs (dual-HPIA mode) from the

perspective of the Host. The ARM/C64x+ can access HPIAW and HPIAR independently. For more details about the HPIA registers and

their modes, see the TMS320DM646x DMSoC Host Port Interface (HPI) User's Guide (literature number SPRUES1).

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