TMS320DM6467_08 Datasheet, PDF (243/340 Pages) Texas Instruments – Digital Media System-on-Chip

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TMS320DM6467
Digital Media System-on-Chip
SPRS403A – DECEMBER 2007 – REVISED MAY 2008
Table 6-56. Ethernet MAC (EMAC) Control Registers (continued)
HEX ADDRESS RANGE
0x01C8 0158
0x01C8 015C
0x01C8 0160
0x01C8 0164
0x01C8 0168
0x01C8 016C
0x01C8 0170
0x01C8 0174
0x01C8 0178 - 0x01C8 01CF
0x01C8 01D0
0x01C8 01D4
0x01C8 01D8
0x01C8 01DC
0x01C8 01E0
0x01C8 01E4
0x01C8 01E8
0x01C8 01EC
0x01C8 01F0 - 0x01C8 01FF
0x01C8 0200 - 0x01C8 02FF
0x01C8 0300 - 0x01C8 04FF
0x01C8 0500
0x01C8 0504
0x01C8 0508
0x01C8 050C - 0x01C8 05FF
0x01C8 0600
0x01C8 0604
0x01C8 0608
0x01C8 060C
0x01C8 0610
0x01C8 0614
0x01C8 0618
0x01C8 061C
0x01C8 0620
0x01C8 0624
0x01C8 0628
0x01C8 062C
0x01C8 0630
0x01C8 0634
0x01C8 0638
0x01C8 063C
0x01C8 0640
0x01C8 0644
0x01C8 0648
0x01C8 064C
ACRONYM
RX6FREEBUFFER
RX7FREEBUFFER
MACCONTROL
MACSTATUS
EMCONTROL
FIFOCONTROL
MACCONFIG
SOFTRESET
–
MACSRCADDRLO
MACSRCADDRHI
MACHASH1
MACHASH2
BOFFTEST
TPACETEST
RXPAUSE
TXPAUSE
–
(see Table 6-57)
–
MACADDRLO
MACADDRHI
MACINDEX
–
TX0HDP
TX1HDP
TX2HDP
TX3HDP
TX4HDP
TX5HDP
TX6HDP
TX7HDP
RX0HDP
RX1HDP
RX2HDP
RX3HDP
RX4HDP
RX5HDP
RX6HDP
RX7HDP
TX0CP
TX1CP
TX2CP
TX3CP
REGISTER NAME
Receive channel 6 free buffer count register
Receive channel 7 free buffer count register
MAC control register
MAC status register
Emulation control register
FIFO control register (transmit and receive)
MAC configuration register
Soft reset register
Reserved
MAC source address low bytes register (lower 16-bits)
MAC source address high bytes register (upper 32-bits)
MAC hash address register 1
MAC hash address register 2
Back off test register
Transmit pacing algorithm test register
Receive pause timer register
Transmit pause timer register
Reserved
EMAC statistics registers
Reserved
MAC address low bytes register (used in receive address matching)
MAC address high bytes register (used in receive address matching)
MAC index register
Reserved
Transmit channel 0 DMA head descriptor pointer register
Transmit channel 1 DMA head descriptor pointer register
Transmit channel 2 DMA head descriptor pointer register
Transmit channel 3 DMA head descriptor pointer register
Transmit channel 4 DMA head descriptor pointer register
Transmit channel 5 DMA head descriptor pointer register
Transmit channel 6 DMA head descriptor pointer register
Transmit channel 7 DMA head descriptor pointer register
Receive channel 0 DMA head descriptor pointer register
Receive channel 1 DMA head descriptor pointer register
Receive channel 2 DMA head descriptor pointer register
Receive channel 3 DMA head descriptor pointer register
Receive channel 4 DMA head descriptor pointer register
Receive channel 5 DMA head descriptor pointer register
Receive channel 6 DMA head descriptor pointer register
Receive channel 7 DMA head descriptor pointer register
Transmit channel 0 completion pointer (interrupt acknowledge)
register
Transmit channel 1 completion pointer (interrupt acknowledge)
register
Transmit channel 2 completion pointer (interrupt acknowledge)
register
Transmit channel 3 completion pointer (interrupt acknowledge)
register
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