TMS320DM6467_08 Datasheet, PDF (155/340 Pages) Texas Instruments – Digital Media System-on-Chip

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TMS320DM6467
Digital Media System-on-Chip
SPRS403A – DECEMBER 2007 – REVISED MAY 2008
6.5 Clock PLLs
There are two independently controlled PLLs on DM6467. PLL1 generates the frequencies required for the
ARM, DSP, HDVICP0/1, EDMA, and peripherals. PLL2 generates the frequencies required for the DDR2
interface. The recommended reference clock for both PLLs is the 27-MHz crystal input. The DM6467 has
a third PLL that is embedded within the USB2.0 PHY and the 24-MHz oscillator is its reference clock
source. This particular PLL is only usable for USB operation, and is discussed further in the
TMS320DM646x DMSoC Universal Serial Bus (USB) Controller User's Guide (literature number
SPRUER7).
6.5.1 PLL1 and PLL2
Both PLL1 and PLL2 power are supplied externally via the 1.8-V PLL power-supply pins (PLL1V_DD18 and
PLL2V_DD18). An external EMI filter circuit must be added to PLL1V_DD18 and PLL2V_DD18, as shown in
Figure 6-11. The 1.8-V supply of the EMI filters must be from the same 1.8-V power plane supplying the
device’s 1.8-V I/O power-supply pins (DV_DDR2). TI recommends EMI filter manufacturer Murata, part
number NFM18CC222R1C3.
All PLL external components (C1, C2, C3, C4, and the EMI Filters) must be placed as close to the device
as possible. For the best performance, TI recommends that all the PLL external components be on a
single side of the board without jumpers, switches, or components other than the ones shown in
Figure 6-11. For reduced PLL jitter, maximize the spacing between switching signals and the PLL external
components (C1, C2, C3, C4, and the EMI Filters).
DM646x
+1.8 V
EMI Filter
C3
C4
0.1μF 0.01μF
PLL1V_DD18
PLL1
+1.8 V
EMI Filter
C1
C2
0.1μF 0.01μF
PLL2V_DD18
PLL2
Figure 6-11. PLL1 and PLL2 External Connection
The minimum CLKIN rise and fall times should also be observed. For the input clock timing requirements,
see Section 6.5.5, Clock PLL Electrical Data/Timing (Input and Output Clocks).
There is an allowable range for PLL multiplier (PLLM). There is a minimum and maximum operating
frequency for DEV_MXI/DEV_CLKIN, PLLOUT, AUX_MXI/AUX_CLKIN, and the device clocks
(SYSCLKs). The PLL Controllers must be configured not to exceed any of these constraints documented
in this section (certain combinations of external clock inputs, internal dividers, and PLL multiply ratios
might not be supported). For these constraints (ranges), see Table 6-7 through Table 6-9.
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Peripheral Information and Electrical Specifications 155