TMS320DM6467_08 Datasheet, PDF (285/340 Pages) Texas Instruments – Digital Media System-on-Chip

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6.20 VLYNQ
TMS320DM6467
Digital Media System-on-Chip
SPRS403A – DECEMBER 2007 – REVISED MAY 2008
The DM6467 VLYNQ peripheral provides a high speed serial communications interface with the following
features.
• Low Pin Count
• Scalable Performance/Support
• Simple Packet Based Transfer Protocol for Memory Mapped Access
– Write Request/Data Packet
– Read Request Packet
– Read Response Data Packet
– Interrupt Request Packet
• Supports both Symmetric and Asymmetric Operation
– Tx pins on first device connect to Rx pins on second device and vice versa
– Data pin widths are automatically detected after reset
– Request packets, response packets, and flow control information are all multiplexed and sent
across the same physical pins
– Supports both Host/Peripheral and Peer-to-Peer communication
• Simple Block Code Packet Formatting (8-bit/10-bit)
• In Band Flow Control
– No extra pins needed
– Allows receiver to momentarily throttle back transmitter when overflow is about to occur
– Uses built in special code capability of block code to seamlessly interleave flow control information
with user data
– Allows system designer to balance cost of data buffering versus performance
• Multiple outstanding transactions
• Automatic packet formatting optimizations
• Internal loop-back mode
6.20.1 VLYNQ Bus Master Memory Map
The VLYNQ peripheral includes a bus master interface that allows external device initiated transfers to
access the DM6467 system bus. Table 6-83 shows the memory map for the VLYNQ master interface.
START ADDRESS
0x0000 0000
0x01C0 0000
0x1000 0000
0x1001 0000
0x1001 4000
0x1001 8000
Table 6-83. VLYNQ Master Memory Map
END ADDRESS
0x01BF FFFF
0x0FFF FFFF
0x1000 FFFF
0x1001 3FFF
0x1001 7FFF
0x1001 FFFF
SIZE
(BYTES)
28M
228M
64K
16K
16K
32K
HPI ACCESS
Reserved
CFG Bus Peripherals
Reserved
ARM RAM 0 (Data)
ARM RAM 1 (Data)
ARM ROM (Data)
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Peripheral Information and Electrical Specifications 285