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TMS320DM6467CCUT7 Datasheet, PDF (94/355 Pages) Texas Instruments – Digital Media System-on-Chip
TMS320DM6467
SPRS403H – DECEMBER 2007 – REVISED JUNE 2012
www.ti.com
4.3.3 Clock and Oscillator Control
The Clock and Oscillator Control (CLKCTL) register allows the user to disable the OSC pwrdwn and pwr
disable
31
26
25
24
23
20
19
16
RESERVED
OSCPWRDN OSCDIS
RESERVED
CLKOUT
R-0000 00
R/W-0 R/W-1
R-0000
R/W-1000
15
12
11
8
7
RESERVED
AUD_CLK1
R-0000
R/W-0000
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
RESERVED
R-0000
4
3
0
AUD_CLK0
R/W-0000
Figure 4-5. CLKCTL Register [0x01C4 005C]
BIT
31:26
25
24
23:20
19:16
15:12
NAME
RESERVED
OSCPWRDN
OSCDIS
RESERVED
CLKOUT
RESERVED
Table 4-7. CLKCTL Register Bit Descriptions
DESCRIPTION
Reserved. Read returns "0".
Auxiliary Oscillator Powerdown.
This bit controls the internal bias resistor conection.
0 = Internal bias resistor connected (normal operation)
1 = Internal bias resistor disconnected (external bias resistor required or clock input used)
Auxiliary Oscillator Disable.
This bit disables the oscillator.
0 = Oscillator enabled (normal operation).
1 = Oscillator disabled (clock input used or no Auxiliary clock required).
Reserved. Read returns "0".
CLKOUT0 Source.
This field selects the clock source for the CLKOUT0 output.
0000 = Disabled
0001 = PLL1 AUXCLK
0010 = Reserved
0011 = SYSCLK3(1)
0100 = SYSCLK4
0101 = SYSCLK5
0110 = SYSCLK6
0111 = Reserved
1000 = SYSCLK8
1001 = SYSCLK9
1010 = AUX_MXI
1011 = Reserved
1100 = Reserved
1101 = Reserved
1110 = Reserved
1111 = Reserved
Reserved. Read returns "0".
(1) The maximum frequency allowed for the CLKOUT0 pin is 148.5 MHz. For the -729 MHz device, in PLL mode, do not configure the
CLKOUT bits to SYSCLK3 (0011) because the CLKOUT0 source will exceed the maximum frequency limit allowed for CLKOUT0 pin.
For more details on the CLKOUT0 timings, see Table 7-15, Switching Characteristics Over Recommended Operating Conditions for
CLKOUT0.
94
Device Configurations
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