TMS320DM6467CCUT7 Datasheet, PDF (146/355 Pages) Texas Instruments – Digital Media System-on-Chip

TMS320DM6467
SPRS403H – DECEMBER 2007 – REVISED JUNE 2012
www.ti.com
Table 7-2. DM6467 Clock Domains
SUBSYSTEM
CLOCK
DOMAIN
DOMAIN
CLOCK
SOURCE
FIXED RATIO vs.
SYSCLK1
FREQUENCY
CLOCK MODES FREQUENCY (MHz)
BYPASS MODE
PLL MODE (-
594) ⁽¹⁾
PLL MODE (-
729) ⁽²⁾
DSP Subsystem
PLLDIV1
PLLC1
SYSCLK1
1:1
27 MHz
594 MHz
729 MHz
ARM926 Subsystem,
1:2
EDMA3, HDVICP, PCI,
VDCE, VPIF, TSIFs,
PLLDIV2
PLLC1
SYSCLK2
13.5 MHz
297 MHz
364.5 MHz
DDR2 Mem Ctlr
Peripherals (GPIO,
Timers, I2C, PWMs, HPI,
EMAC, EMIFA, VLYNQ,
SPI, ARM INTC, USB2.0,
UARTs, McASPs,
CRGENs, SYSTEM)
ATA
TSIF0 ⁽⁴⁾
TSIF1 ⁽⁴⁾
VPIF ⁽⁴⁾
VLYNQ
PLLDIV3
PLLDIV4
PLLDIV5
PLLDIV6
PLLDIV8
PLLDIV9
1:4
PLLC1
SYSCLK3
6.75 MHz
PLLC1
SYSCLK4
PLLC1
SYSCLK5
PLLC1
SYSCLK6
PLLC1
SYSCLK8
PLLC1
SYSCLK9
1:6 (-594) [default]⁽³⁾
1:7 (-729)⁽³⁾
1:8 (-594) [default]⁽³⁾
1:10 (-729)⁽³⁾
1:8 (-594) [default]⁽³⁾
1:10 (-729)⁽³⁾
1:6 (-594) [default]⁽³⁾
1:7 (-729)⁽³⁾
1:6 (-594) [default]⁽³⁾
1:7 (-729)⁽³⁾
4.5 MHz
3.38 MHz
3.38 MHz
3.38 MHz
4.5 MHz
148.5 MHz
182.25 MHz
99 MHz
74.25 MHz
74.25 MHz
99 MHz
99 MHz
104.14 MHz
72.9 MHz
72.9 MHz
104.14 MHz⁽⁵⁾
104.14 MHz
DDR2 PHY
PLLDIV1
PLLC2
SYSCLK1
1:1
27 MHz
594 MHz
621 MHz
(1) These table values assume a DEV_MXI/DEV_CLKIN of 27 MHz and a PLL1 multiplier equal to 22.
(2) These table values assume a DEV_MXI/DEV_CLKIN of 27 MHz and a PLL1 multiplier equal to 27.
(3) The default SYSCLKx ratios apply to the -594 MHz device only. For the -729 MHz device to achieve the quoted frequencines, the
PLLC1 SYSCLKx (for SYSCLK4, SYSCLK5, SYSCLK6, SYSCLK8, SYSCLK9) default divider values must be changed. For the steps to
change the PLLC1 SYSCLKx divider values, see theTMS320DM646x DMSoC ARM Subsystem Reference Guide (literature number
SPRUEP9).
(4) These domain clock sources, along with VP_CLKIN[3:0], STC_CLKIN, CRG0_VCXI, and CRG1_VCXI clock signals, go through the
clock select logic to determine the clock source enabled as the input to the VPIF and TSIF peripherals.
(5) For the -729 device, use an external clock source for the 54-/74.25-/108-MHz VPIF clock.
146 Peripheral Information and Electrical Specifications
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