TMS320DM6467CCUT7 Datasheet, PDF (344/355 Pages) Texas Instruments – Digital Media System-on-Chip

TMS320DM6467
SPRS403H – DECEMBER 2007 – REVISED JUNE 2012
www.ti.com
7.28 General-Purpose Input/Output (GPIO)
The GPIO peripheral provides general-purpose pins that can be configured as either inputs or outputs.
When configured as an output, a write to an internal register can control the state driven on the output pin.
When configured as an input, the state of the input is detectable by reading the state of an internal
register. In addition, the GPIO peripheral can produce CPU interrupts and EDMA events in different
interrupt/event generation modes. The GPIO peripheral provides generic connections to external devices.
The GPIO pins are grouped into banks of 16 pins per bank (i.e., bank 0 consists of GP[0:15]).
7.28.1 GPIO Device-Specific Information
The DM6467 GPIO peripheral supports the following:
• Up to 33 3.3-V GPIO pins, GP[0:47; not all pinned out]
• Interrupts:
– Up to 8 unique GP[0:7] interrupts from Bank 0
– 3 GPIO bank (aggregated) interrupt signals from each of the 3 banks of GPIOs
– Interrupts can be triggered by rising and/or falling edge, specified for each interrupt capable GPIO
signal
• DMA events:
– Up to 8 unique GPIO DMA events from Bank 0
– 3 GPIO bank (aggregated) DMA event signals from each of the 3 banks of GPIOs
• Set/clear functionality: Software writes 1 to corresponding bit position(s) to set or to clear GPIO
signal(s). This allows multiple software processes to toggle GPIO output signals without critical section
protection (disable interrupts, program GPIO, re-enable interrupts, to prevent context switching to
anther process during GPIO programming).
• Separate Input/Output registers
• Output register in addition to set/clear so that, if preferred by software, some GPIO output signals can
be toggled by direct write to the output register(s).
• Output register, when read, reflects output drive status. This, in addition to the input register reflecting
pin status and open-drain I/O cell, allows wired logic be implemented.
Although, the DM6467 device implements three GPIO banks, not all GPIOs from all banks are available
externally (pinned out). The following GPIOs are not pinned out on the DM6467 device:
• BANK 0
– GP[9]
– GP[14]
– GP[15]
• BANK 1
– GP[27:31]
• BANK 2
• GP[34]
• GP[35]
• GP[43:47]
For more detailed information on GPIOs, see the TMS320DM646x DMSoC General-Purpose Input/Output
(GPIO) User's Guide (literature number SPRUEQ8).
344 Peripheral Information and Electrical Specifications
Copyright © 2007–2012, Texas Instruments Incorporated
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