TMS320DM6467CCUT7 Datasheet, PDF (201/355 Pages) Texas Instruments – Digital Media System-on-Chip

TMS320DM6467
www.ti.com
SPRS403H – DECEMBER 2007 – REVISED JUNE 2012
7.9 External Memory Interface (EMIF)
DM6467 supports several memory and external device interfaces, including:
• Asynchronous EMIF (EMIFA) for interfacing to NOR Flash, SRAM, etc.
• NAND Flash
• ATA (see Section 7.20, ATA Controller)
7.9.1 Asynchronous EMIF (EMIFA)
The DM6467 Asynchronous EMIF (EMIFA) provides an 8-bit or 16-bit data bus, an address bus width up
to 24 bits, and 4 chip selects, along with memory control signals. These signals are multiplexed between
these peripherals:
• EMIFA and NAND interfaces
• ATA interface
• Host-Port Interface (HPI)
• PCI
• GPIO
7.9.2 NAND (NAND, SmartMedia/SSFDC, xD)
The EMIFA interface provides both the asynchronous EMIF and NAND interfaces. Four chip selects are
provided and each are individually configurable to provide either EMIFA or NAND support. The NAND
features supported are as follows.
• NAND flash on up to 4 asynchronous chip selects
• 8- or 16-bit data bus width
• Programmable cycle timings
• Performs ECC calculation
• NAND Mode also supports SmartMedia/SSFDC (Solid State Floppy Disk Controller) and xD memory
cards
• ARM ROM supports booting of the DM6467 ARM926 processor from NAND flash located at CS2
The memory map for EMIFA and NAND registers is shown in Table 7-28. For more details on the EMIFA
and NAND interfaces, the TMS320DM646x DMSoC Asynchronous External Memory Interface (EMIF)
User's Guide (literature number SPRUEQ7).
7.9.3 EMIFA Peripheral Register Description(s)
Table 7-28 shows the EMIFA/NAND registers.
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Peripheral Information and Electrical Specifications 201
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