TMS320DM6467CCUT7 Datasheet, PDF (157/355 Pages) Texas Instruments – Digital Media System-on-Chip

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TMS320DM6467
SPRS403H – DECEMBER 2007 – REVISED JUNE 2012
Table 7-8. PLL1 and PLL2 Multiplier Ranges
PLL MULTIPLIER
(PLLM)
PLL1 Multiplier
PLL2 Multiplier
-594
MIN
MAX
x14
x22
x14
x22
-729
MIN
MAX
x14
x27
x14
x23
Table 7-9. PLLC1 Clock Frequency Ranges
CLOCK SIGNAL NAME
DEV_MXI/DEV_CLKIN ⁽¹⁾
-594
MIN
MAX
20
30
-729
MIN
MAX
20
30
PLLOUT
400
594
400
729
SYSCLK1 (PLLDIV1 Domain)
594
729
(1) DEV_MXI/DEV_CLKIN input clock is used for both PLL Controllers (PLLC1 and PLLC2).
UNIT
MHz
MHz
MHz
Table 7-10. PLLC2 Clock Frequency Ranges
CLOCK SIGNAL NAME
DEV_MXI/DEV_CLKIN ⁽¹⁾
-594
MIN
MAX
20
30
-729
MIN
MAX
20
30
PLLOUT
400
594
400
621
PLL2_SYSCLK1 (to DDR2 PHY)
594
621
(1) DEV_MXI/DEV_CLKIN input clock is used for both PLL Controllers (PLLC1 and PLLC2).
UNIT
MHz
MHz
MHz
Both PLL1 and PLL2 have stabilization, lock, and reset timing requirements that must be followed.
The PLL stabilization time is the amount of time that must be allotted for the internal PLL regulators to
become stable after the PLL is powered up (after the PLLCTL.PLLPWRDN bit goes through a 1-to-0
transition). The PLL should not be operated until this stabilization time has expired. This stabilization step
must be applied after these resets—a Power-on Reset, a Warm Reset, or a Max Reset, as the
PLLCTL.PLLPWRDN bit resets to a "1". For the PLL stabliziation time value, see Table 7-11.
The PLL reset time is the amount of wait time needed for the PLL to properly reset (writing PLLRST = 1)
before bringing the PLL out of reset (writing PLLRST = 0). For the PLL reset time value, see Table 7-11.
The PLL lock time is the amount of time needed from when the PLL is taken out of reset (PLLRST = 0
with PLLEN = 0) to when to when the PLL controller can be switched to PLL mode (PLLEN = 1). For the
PLL lock time value, see Table 7-11.
Table 7-11. PLL1 and PLL2 Stabilization, Lock, and Reset Times
PLL STABILIZATION/
LOCK/RESET TIME
MIN
NOM
MAX
UNIT
PLL Stabilization Time
PLL Lock Time
PLL Reset Time
150
128C ⁽¹⁾
μs
2000C ⁽¹⁾
ns
ns
(1) C = CLKIN cycle time in ns. For example, when DEV_MXI/DEV_CLKIN or AUX_MXI/AUX_CLKIN
frequency is 27 MHz, use C = 37.037 ns.
For details on the PLL initialization software sequence, see the TMS320DM646x DMSoC ARM Subsystem
Reference Guide (literature number SPRUEP9).
For more information on the clock domains and their clock ratio restrictions, see Section 7.3.4, DM6467
Power and Clock Domains.
Copyright © 2007–2012, Texas Instruments Incorporated
Peripheral Information and Electrical Specifications 157
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