TMS320DM6467CCUT7 Datasheet, PDF (61/355 Pages) Texas Instruments – Digital Media System-on-Chip

TMS320DM6467
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3.7.18 Clock Recovery Generator (CRGEN)
SPRS403H – DECEMBER 2007 – REVISED JUNE 2012
Table 3-22. Clock Recovery Generator (CRGEN) Terminal Functions
SIGNAL
NAME
TYPE ⁽¹⁾
NO.
OTHER ^{(2) (3)}
DESCRIPTION
CRGEN1 ONLY MODE (PINMUX0.CRGMUX = 001)
URXD2/
CRG1_VCXI/
GP[39]/
CRG0_VCXI
AB20 I/O/Z
IPD
DV_DD33
This pin is multiplexed between UART2, CRGEN1, GPIO, and CRGEN0.
When CRGEN1 is enabled (PINMUX0.CRGMUX = 001), this pin is CRGEN1 input
clock from external VCXO, CRG1_VCXI (I).
UTXD2/ URCTX2/
CRG1_PO/
GP[40]/
CRG0_PO
AA19
I/O/Z
IPD
DV_DD33
This pin is multiplexed between UART2, CRGEN1, GPIO, and CRGEN0.
When CRGEN1 is enabled (PINMUX0.CRGMUX = 001), this pin is CRGEN1
pulse width modulation output, CRG1_PO (O/Z).
CRGEN0 ONLY (UART2/PWM0 MUX) MODE (PINMUX0.CRGMUX = 100)
UCTS2/ USD2/
CRG0_VCXI/
GP[42]/
TS1_PSTO
AC21
I/O/Z
IPU
DV_DD33
This pin is multiplexed between UART2, CRGEN0, GPIO, and TSIF1.
When CRGEN0 on UART2/PWM muxing is enabled (PINMUX0.CRGMUX = 10x),
this pin is CRGEN0 input clock from external VCXO, CRG0_VCXI (I).
PWM0/
CRG0_PO/
TS1_ENAO
W17 O/Z
–
DV_DD33
This pin is multiplexed between PWM0, CRGEN0, and TSIF1.
When CRGEN0 on UART2/PWM muxing is enabled (PINMUX0.CRGMUX = 10x),
this pin is CRGEN0 pulse width modulation output, CRG0_PO (O/Z).
CRGEN0 AND CRGEN1 MODE (PINMUX0.CRGMUX = 101)
URXD2/
CRG1_VCXI/
GP[39]/
CRG0_VCXI
AB20 I/O/Z
IPD
DV_DD33
This pin is multiplexed between UART2, CRGEN1, GPIO, and CRGEN0.
When CRGEN1 is enabled (PINMUX0.CRGMUX = x01), this pin is CRGEN1 input
clock from external VCXO, CRG1_VCXI (I).
UTXD2/ URCTX2/
CRG1_PO/
GP[40]/
CRG0_PO
AA19
I/O/Z
IPD
DV_DD33
This pin is multiplexed between UART2, CRGEN1, GPIO, and CRGEN0.
When CRGEN1 is enabled (PINMUX0.CRGMUX = x01), this pin is CRGEN1
pulse width modulation output, CRG1_PO (O/Z).
UCTS2/ USD2/
CRG0_VCXI/
GP[42]/
TS1_PSTO
AC21
I/O/Z
IPU
DV_DD33
This pin is multiplexed between UART2, CRGEN0, GPIO, and TSIF1.
When CRGEN0 on UART2/PWM muxing is enabled (PINMUX0.CRGMUX = 10x),
this pin is CRGEN0 input clock from external VCXO, CRG0_VCXI (I).
PWM0/
CRG0_PO/
TS1_ENAO
W17 O/Z
–
DV_DD33
This pin is multiplexed between PWM0, CRGEN0, and TSIF1.
When CRGEN0 on UART2/PWM muxing is enabled (PINMUX0.CRGMUX = 10x),
this pin is CRGEN0 pulse width modulation output, CRG0_PO (O/Z).
CRGEN0 ONLY (UART2 MUX) MODE (PINMUX0.CRGMUX = 110)
URXD2/
CRG1_VCXI/
GP[39]/
CRG0_VCXI
AB20 I/O/Z
IPD
DV_DD33
This pin is multiplexed between UART2, CRGEN1, GPIO, and CRGEN0.
When CRGEN0 on UART2 muxing is enabled (PINMUX0.CRGMUX = 110), this
pin is CRGEN0 input clock from external VCXO, CRG0_VCXI (I).
UTXD2/ URCTX2/
CRG1_PO/
GP[40]/
CRG0_PO
AA19
I/O/Z
IPD
DV_DD33
This pin is multiplexed between UART2, CRGEN1, GPIO, and CRGEN0.
When CRGEN0 on UART2 muxing is enabled (PINMUX0.CRGMUX = 110), this
pin is CRGEN0 pulse width modulation output, CRG0_PO (O/Z).
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
(2) IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external
pullup/pulldown resistors are required, see Section 4.8.1, Pullup/Pulldown Resistors.
(3) Specifies the operating I/O supply voltage for each signal
Copyright © 2007–2012, Texas Instruments Incorporated
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