AM1808_11 Datasheet, PDF(93/262 Page) Texas Instruments – AM1808 ARM Microprocessor

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AM1808_11 Datasheet, PDF (93/262 Pages) Texas Instruments – AM1808 ARM Microprocessor

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AM1808

www.ti.com

SPRS653C â FEBRUARY 2010 â REVISED DECEMBER 2011

Table 5-13. EDMA3 Channel Controller (EDMA3CC) Registers (continued)

EDMA0 Channel EDMA1 Channel

Controller 0

Controller 0

BYTE ADDRESS BYTE ADDRESS

0x01C0 2208

0x01E3 2208

0x01C0 2210

0x01E3 2210

0x01C0 2218

0x01E3 2218

0x01C0 2220

0x01E3 2220

0x01C0 2228

0x01E3 2228

0x01C0 2230

0x01E3 2230

0x01C0 2238

0x01E3 2238

0x01C0 2240

0x01E3 2240

0x01C0 2250

0x01E3 2250

0x01C0 2258

0x01E3 2258

0x01C0 2260

0x01E3 2260

0x01C0 2268

0x01E3 2268

0x01C0 2270

0x01E3 2270

0x01C0 2278

0x01E3 2278

0x01C0 2280

0x01E3 2280

0x01C0 2284

0x01E3 2284

0x01C0 2288

0x01E3 2288

0x01C0 228C

0x01E3 228C

0x01C0 2290

0x01E3 2290

0x01C0 2294

0x01E3 2294

0x01C0 4000 -

0x01C0 4FFF

0x01E3 4000 -

0x01E3 4FFF

ACRONYM

ECR

ESR

CER

EER

EECR

EESR

SER

SECR

IER

IECR

IESR

IPR

ICR

IEVAL

QER

QEER

QEECR

QEESR

QSER

QSECR

â

REGISTER DESCRIPTION

Event Clear Register

Event Set Register

Chained Event Register

Event Enable Register

Event Enable Clear Register

Event Enable Set Register

Secondary Event Register

Secondary Event Clear Register

Interrupt Enable Register

Interrupt Enable Clear Register

Interrupt Enable Set Register

Interrupt Pending Register

Interrupt Clear Register

Interrupt Evaluate Register

QDMA Event Register

QDMA Event Enable Register

QDMA Event Enable Clear Register

QDMA Event Enable Set Register

QDMA Secondary Event Register

QDMA Secondary Event Clear Register

Parameter RAM (PaRAM)

Table 5-14. EDMA3 Transfer Controller (EDMA3TC) Registers

EDMA0

Transfer Controller

0

BYTE ADDRESS

EDMA0

Transfer Controller

1

BYTE ADDRESS

EDMA1

Transfer Controller

0

BYTE ADDRESS

0x01C0 8000

0x01C0 8400

0x01E3 8000

0x01C0 8004

0x01C0 8404

0x01E3 8004

0x01C0 8100

0x01C0 8500

0x01E3 8100

0x01C0 8120

0x01C0 8520

0x01E3 8120

0x01C0 8124

0x01C0 8524

0x01E3 8124

0x01C0 8128

0x01C0 8528

0x01E3 8128

0x01C0 812C

0x01C0 852C

0x01E3 812C

0x01C0 8130

0x01C0 8530

0x01E3 8130

0x01C0 8140

0x01C0 8540

0x01E3 8140

0x01C0 8240

0x01C0 8640

0x01E3 8240

0x01C0 8244

0x01C0 8644

0x01E3 8244

0x01C0 8248

0x01C0 8648

0x01E3 8248

0x01C0 824C

0x01C0 864C

0x01E3 824C

0x01C0 8250

0x01C0 8650

0x01E3 8250

0x01C0 8254

0x01C0 8654

0x01E3 8254

0x01C0 8258

0x01C0 8658

0x01E3 8258

0x01C0 825C

0x01C0 865C

0x01E3 825C

0x01C0 8260

0x01C0 8660

0x01E3 8260

ACRONYM

PID

TCCFG

TCSTAT

ERRSTAT

ERREN

ERRCLR

ERRDET

ERRCMD

RDRATE

SAOPT

SASRC

SACNT

SADST

SABIDX

SAMPPRXY

SACNTRLD

SASRCBREF

SADSTBREF

REGISTER DESCRIPTION

Peripheral Identification Register

EDMA3TC Configuration Register

EDMA3TC Channel Status Register

Error Status Register

Error Enable Register

Error Clear Register

Error Details Register

Error Interrupt Command Register

Read Command Rate Register

Source Active Options Register

Source Active Source Address Register

Source Active Count Register

Source Active Destination Address Register

Source Active B-Index Register

Source Active Memory Protection Proxy Register

Source Active Count Reload Register

Source Active Source Address B-Reference Register

Source Active Destination Address B-Reference

Register

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Peripheral Information and Electrical Specifications

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