AM1808_11 Datasheet, PDF (17/262 Pages) Texas Instruments – AM1808 ARM Microprocessor

AM1808
www.ti.com
SPRS653C – FEBRUARY 2010 – REVISED DECEMBER 2011
AB
DC
1
2
3
4
5
6
7
8
9
10
VP_CLKIN3/
PRU0_R30[23]/
MMCSD1_DAT[1]/ MMCSD1_CMD/
J
SATA_TXP
SATA_TXN
PRU1_R30[1]/ UPP_CHB_ENABLE/ DVDD3318_C
CVDD
VSS
VSS
VSS
VSS
J
GP6[2]/
GP8[13]/
PRU1_R31[2]
PRU1_R31[25]
VP_CLKIN2/
MMCSD1_DAT[5]/
MMCSD1_DAT[3]/
LCD_HSYNC/
H
SATA_VSS
SATA_VSS
PRU1_R30[3]/
PRU1_R30[5]/
DVDD3318_A
CVDD
CVDD
VSS
GP6[4]/
GP8[9]/
PRU1_R31[4]
PRU1_R31[6]
VSS
CVDD
H
PRU0_R30[25]/
PRU0_R30[24]/
PRU0_R30[22]/ MMCSD1_DAT[4]/
MMCSD1_DAT[0]/ MMCSD1_CLK/
PRU1_R30[8]/
LCD_VSYNC/
G UPP_CHB_CLOCK/ UPP_CHB_START/ UPP_CHB_WAIT/
GP8[15]/
GP8[14]/
GP8[12]/
PRU1_R30[4]/
GP8[8]/
PRU1_R31[27]
PRU1_R31[26]
PRU1_R31[24]
PRU1_R31[5]
DVDD3318_A
DVDD18
CVDD
CVDD
DVDD3318_B
DVDD18
G
F
MMCSD1_DAT[7]/
LCD_PCLK/
PRU1_R30[7]/
GP8[11]
MMCSD1_DAT[6]/
LCD_MCLK/
PRU1_R30[6]/
GP8[10]/
PRU1_R31[7]
AXR0/
ECAP0_APWM0/
GP8[7]/
MII_TXD[0]/
CLKS0
RTC_ALARM/
UART2_CTS/
GP0[8]/
DEEPSLEEP
DVDD3318_A
DVDD3318_B
DVDD3318_B
DVDD3318_B
EMA_CS[4]/
GP3[13]
DVDD3318_B
F
AXR1/
DX0/
E
GP1[9]/
MII_TXD[1]
AXR2/
DR0/
GP1[10]/
MII_TXD[2]
AXR3/
FSX0/
GP1[11]/
MII_TXD[3]
AXR8/
CLKS1/
ECAP1_APWM1/
GP0[0]/
PRU0_R31[8]
RVDD
EMA_D[15]/
GP3[7]
EMA_D[5]/
GP4[13]
EMA_D[3]/
GP4[11]
MMCSD0_CLK/
PRU1_R30[31]/
GP4[7]
EMA_D[8]/
GP3[0]
E
D
AXR4/
FSR0/
GP1[12]/
MII_COL
AXR7/
EPWM1TZ[0]/
PRU0_R30[17]
GP1[15]/
PRU0_R31[7]
AXR5/
CLKX0/
GP1[13]/
MII_TXCLK
AXR10/
DR1/
GP0[2]
AMUTE/
PRU0_R30[16]/
UART2_RTS/
GP0[9]/
PRU0_R31[16]
EMA_D[11]/
GP3[3]
EMA_D[7]/
GP4[15]
EMA_SDCKE/
PRU0_R30[4]/
GP2[6]/
PRU0_R31[4]
EMA_D[9]/
GP3[1]
EMA_A_RW/
GP3[9]
D
AXR6/
CLKR0/
AFSR/
C
GP1[14]/
GP0[13]/
MII_TXEN/
PRU0_R31[20]
PRU0_R31[6]
AXR9/
DX1/
GP0[1]
AXR12/
FSR1/
GP0[4]
AXR11/
FSX1/
GP0[3]
EMA_D[6]/
GP4[14]
EMA_A[19]/
EMA_D[14]/
EMA_WEN_DQM[0]/
EMA_D[0]/
MMCSD0_DAT[2]/
GP3[6]
GP2[3]
GP4[8]
PRU1_R30[27]/
C
GP4[3]
B
ACLKX/
PRU0_R30[19]/
GP0[14]/
PRU0_R31[21]
AFSX/
GP0[12]/
PRU0_R31[19]
AXR13/
CLKX1/
GP0[5]
AXR14/
CLKR1/
GP0[6]
EMA_D[4]/
GP4[12]
EMA_D[13]/
GP3[5]
EMA_CLK/
PRU0_R30[5]/
GP2[7]/
PRU0_R31[5]
EMA_D[2]/
GP4[10]
EMA_A[21]/
EMA_WE/
GP3[11]
MMCSD0_DAT[0]/
PRU1_R30[29]/
B
GP4[5]
A
ACLKR/
PRU0_R30[20]/
GP0[15]/
PRU0_R31[22]
AHCLKR/
PRU0_R30[18]/
UART1_RTS/
GP0[11]/
PRU0_R31[18]
AHCLKX/
USB_REFCLKIN/
UART1_CTS/
GP0[10]/
PRU0_R31[17]
AXR15/
EPWM0TZ[0]/
ECAP2_APWM2/
GP0[7]
EMA_WEN_DQM[1]/
GP2[2]
EMA_D[12]/
GP3[4]
EMA_D[10]/
GP3[2]
EMA_D[1]/
GP4[9]
EMA_CAS/
EMA_A[22]/
PRU0_R30[2]/
GP2[4]/
MMCSD0_CMD/
PRU1_R30[30]/
A
PRU0_R31[2]
GP4[6]
1
2
3
4
5
6
7
8
9
10
Figure 2-4. Pin Map (Quad D)
2.6 Pin Multiplexing Control
Device level pin multiplexing is controlled by registers PINMUX0 - PINMUX19 in the SYSCFG module.
For the device family, pin multiplexing can be controlled on a pin-by-pin basis. Each pin that is multiplexed
with several different functions has a corresponding 4-bit field in one of the PINMUX registers.
Pin multiplexing selects which of several peripheral pin functions controls the pin's IO buffer output data
and output enable values only. The default pin multiplexing control for almost every pin is to select 'none'
of the peripheral functions in which case the pin's IO buffer is held tri-stated.
Note that the input from each pin is always routed to all of the peripherals that share the pin; the PINMUX
registers have no effect on input from a pin.
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