AM1808_11 Datasheet, PDF (145/262 Pages) Texas Instruments – AM1808 ARM Microprocessor

AM1808
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SPRS653C – FEBRUARY 2010 – REVISED DECEMBER 2011
Table 5-61. Timing Requirements for McBSP1 [1.3V, 1.2V, 1.1V]⁽¹⁾ (see Figure 5-32)
NO.
PARAMETER
2 t_c(CKRX)
3 t_w(CKRX)
5 t_su(FRH-CKRL)
6 t_h(CKRL-FRH)
7 t_su(DRV-CKRL)
8 t_h(CKRL-DRV)
10 t_su(FXH-CKXL)
11 t_h(CKXL-FXH)
Cycle time, CLKR/X
CLKR/X ext
Pulse duration, CLKR/X high or
CLKR/X low
CLKR/X ext
Setup time, external FSR high before ^{CLKR int}
CLKR low
CLKR ext
Hold time, external FSR high after
CLKR low
CLKR int
CLKR ext
CLKR int
Setup time, DR valid before CLKR low
CLKR ext
Hold time, DR valid after CLKR low
CLKR int
CLKR ext
Setup time, external FSX high before ^{CLKX int}
CLKX low
CLKX ext
Hold time, external FSX high after
CLKX low
CLKX int
CLKX ext
1.3V, 1.2V
MIN
2P or 20 ⁽²⁾⁽³⁾
MAX
P - 1 ⁽⁵⁾
15
5
6
3
15
5
3
3
15
5
6
3
1.1V
MIN
2P or 25^{(2) (4)}
P - 1 ⁽⁶⁾
18
5
6
3
18
5
3
3
18
5
6
3
MAX
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
(1) CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also
inverted.
(2) P = ASYNC3 period in ns. For example, when the ASYNC clock domain is running at 100 MHz, use 10 ns.
(3) Use whichever value is greater. Minimum CLKR/X cycle times must be met, even when CLKR/X is generated by an internal clock
source. The minimum CLKR/X cycle times are based on internal logic speed; the maximum usable speed may be lower due to EDMA
limitations and AC timing requirements.
(4) Use whichever value is greater. Minimum CLKR/X cycle times must be met, even when CLKR/X is generated by an internal clock
source. The minimum CLKR/X cycle times are based on internal logic speed; the maximum usable speed may be lower due to EDMA
limitations and AC timing requirements.
(5) This parameter applies to the maximum McBSP frequency. Operate serial clocks (CLKR/X) in the reasonable range of 40/60 duty cycle.
(6) This parameter applies to the maximum McBSP frequency. Operate serial clocks (CLKR/X) in the reasonable range of 40/60 duty cycle.
Table 5-62. Timing Requirements for McBSP1 [1.0V]⁽¹⁾ (see Figure 5-32)
NO.
PARAMETER
2 t_c(CKRX)
3 t_w(CKRX)
Cycle time, CLKR/X
Pulse duration, CLKR/X high or CLKR/X low
5 t_su(FRH-CKRL) Setup time, external FSR high before CLKR low
6 t_h(CKRL-FRH) Hold time, external FSR high after CLKR low
7 t_su(DRV-CKRL) Setup time, DR valid before CLKR low
8 t_h(CKRL-DRV) Hold time, DR valid after CLKR low
10 t_su(FXH-CKXL) Setup time, external FSX high before CLKX low
11 t_h(CKXL-FXH) Hold time, external FSX high after CLKX low
CLKR/X ext
CLKR/X ext
CLKR int
CLKR ext
CLKR int
CLKR ext
CLKR int
CLKR ext
CLKR int
CLKR ext
CLKX int
CLKX ext
CLKX int
CLKX ext
1.0V
MIN
2P or 26.6⁽²⁾⁽³⁾
P - 1 ⁽⁴⁾
21
10
6
3
21
10
3
3
21
10
6
3
MAX
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
(1) CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also
inverted.
(2) P = ASYNC3 period in ns. For example, when the ASYNC clock domain is running at 100 MHz, use 10 ns.
(3) Use whichever value is greater. Minimum CLKR/X cycle times must be met, even when CLKR/X is generated by an internal clock
source. The minimum CLKR/X cycle times are based on internal logic speed; the maximum usable speed may be lower due to EDMA
limitations and AC timing requirements.
(4) This parameter applies to the maximum McBSP frequency. Operate serial clocks (CLKR/X) in the reasonable range of 40/60 duty cycle.
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Peripheral Information and Electrical Specifications 145
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