AM1808_11 Datasheet, PDF (142/262 Pages) Texas Instruments – AM1808 ARM Microprocessor

AM1808
SPRS653C – FEBRUARY 2010 – REVISED DECEMBER 2011
www.ti.com
Table 5-58. Timing Requirements for McBSP0 [1.0V]⁽¹⁾ (see Figure 5-32)
NO.
PARAMETER
2 t_c(CKRX)
3 t_w(CKRX)
Cycle time, CLKR/X
Pulse duration, CLKR/X high or CLKR/X low
5 t_su(FRH-CKRL) Setup time, external FSR high before CLKR low
6 t_h(CKRL-FRH) Hold time, external FSR high after CLKR low
7 t_su(DRV-CKRL) Setup time, DR valid before CLKR low
8 t_h(CKRL-DRV) Hold time, DR valid after CLKR low
10 t_su(FXH-CKXL) Setup time, external FSX high before CLKX low
11 t_h(CKXL-FXH) Hold time, external FSX high after CLKX low
CLKR/X ext
CLKR/X ext
CLKR int
CLKR ext
CLKR int
CLKR ext
CLKR int
CLKR ext
CLKR int
CLKR ext
CLKX int
CLKX ext
CLKX int
CLKX ext
1.0V
MIN
2P or 26.6⁽²⁾⁽³⁾
P - 1 ⁽⁴⁾
20
5
6
3
20
5
3
3
20
5
6
3
MAX
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
(1) CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also
inverted.
(2) P = ASYNC3 period in ns. For example, when the ASYNC clock domain is running at 100 MHz, use 10 ns.
(3) Use whichever value is greater. Minimum CLKR/X cycle times must be met, even when CLKR/X is generated by an internal clock
source. The minimum CLKR/X cycle times are based on internal logic speed; the maximum usable speed may be lower due to EDMA
limitations and AC timing requirements.
(4) This parameter applies to the maximum McBSP frequency. Operate serial clocks (CLKR/X) in the reasonable range of 40/60 duty cycle.
142 Peripheral Information and Electrical Specifications
Copyright © 2010–2011, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): AM1808