AM1808_11 Datasheet, PDF (184/262 Pages) Texas Instruments – AM1808 ARM Microprocessor

AM1808
SPRS653C – FEBRUARY 2010 – REVISED DECEMBER 2011
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5.22 Ethernet Media Access Controller (EMAC)
The Ethernet Media Access Controller (EMAC) provides an efficient interface between device and the
network. The EMAC supports both 10Base-T and 100Base-TX, or 10 Mbits/second (Mbps) and 100 Mbps
in either half- or full-duplex mode, with hardware flow control and quality of service (QOS) support.
The EMAC controls the flow of packet data from the device to the PHY. The MDIO module controls PHY
configuration and status monitoring.
Both the EMAC and the MDIO modules interface to the device through a custom interface that allows
efficient data transmission and reception. This custom interface is referred to as the EMAC control
module, and is considered integral to the EMAC/MDIO peripheral. The control module is also used to
multiplex and control interrupts.
5.22.1 EMAC Peripheral Register Description(s)
Table 5-94. Ethernet Media Access Controller (EMAC) Registers
BYTE ADDRESS
0x01E2 3000
0x01E2 3004
0x01E2 3008
0x01E2 3010
0x01E2 3014
0x01E2 3018
0x01E2 3080
0x01E2 3084
0x01E2 3088
0x01E2 308C
0x01E2 3090
0x01E2 3094
0x01E2 30A0
0x01E2 30A4
0x01E2 30A8
0x01E2 30AC
0x01E2 30B0
0x01E2 30B4
0x01E2 30B8
0x01E2 30BC
0x01E2 3100
0x01E2 3104
0x01E2 3108
0x01E2 310C
0x01E2 3110
0x01E2 3114
0x01E2 3120
0x01E2 3124
0x01E2 3128
0x01E2 312C
0x01E2 3130
0x01E2 3134
0x01E2 3138
0x01E2 313C
ACRONYM
REGISTER DESCRIPTION
TXREV
Transmit Revision Register
TXCONTROL
Transmit Control Register
TXTEARDOWN
Transmit Teardown Register
RXREV
Receive Revision Register
RXCONTROL
Receive Control Register
RXTEARDOWN
Receive Teardown Register
TXINTSTATRAW
Transmit Interrupt Status (Unmasked) Register
TXINTSTATMASKED Transmit Interrupt Status (Masked) Register
TXINTMASKSET
Transmit Interrupt Mask Set Register
TXINTMASKCLEAR Transmit Interrupt Clear Register
MACINVECTOR
MAC Input Vector Register
MACEOIVECTOR MAC End Of Interrupt Vector Register
RXINTSTATRAW Receive Interrupt Status (Unmasked) Register
RXINTSTATMASKED Receive Interrupt Status (Masked) Register
RXINTMASKSET
Receive Interrupt Mask Set Register
RXINTMASKCLEAR Receive Interrupt Mask Clear Register
MACINTSTATRAW MAC Interrupt Status (Unmasked) Register
MACINTSTATMASKED MAC Interrupt Status (Masked) Register
MACINTMASKSET MAC Interrupt Mask Set Register
MACINTMASKCLEAR MAC Interrupt Mask Clear Register
RXMBPENABLE
Receive Multicast/Broadcast/Promiscuous Channel Enable Register
RXUNICASTSET
Receive Unicast Enable Set Register
RXUNICASTCLEAR Receive Unicast Clear Register
RXMAXLEN
Receive Maximum Length Register
RXBUFFEROFFSET Receive Buffer Offset Register
RXFILTERLOWTHRESH Receive Filter Low Priority Frame Threshold Register
RX0FLOWTHRESH Receive Channel 0 Flow Control Threshold Register
RX1FLOWTHRESH Receive Channel 1 Flow Control Threshold Register
RX2FLOWTHRESH Receive Channel 2 Flow Control Threshold Register
RX3FLOWTHRESH Receive Channel 3 Flow Control Threshold Register
RX4FLOWTHRESH Receive Channel 4 Flow Control Threshold Register
RX5FLOWTHRESH Receive Channel 5 Flow Control Threshold Register
RX6FLOWTHRESH Receive Channel 6 Flow Control Threshold Register
RX7FLOWTHRESH Receive Channel 7 Flow Control Threshold Register
184 Peripheral Information and Electrical Specifications
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