AM1808_11 Datasheet, PDF (137/262 Pages) Texas Instruments – AM1808 ARM Microprocessor

AM1808
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SPRS653C – FEBRUARY 2010 – REVISED DECEMBER 2011
Table 5-54. Switching Characteristics for McASP0 (1.3V, 1.2V, 1.1V)⁽¹⁾
NO.
9 t_c(AHCLKRX)
10 t_w(AHCLKRX)
11 t_c(ACLKRX)
12 t_w(ACLKRX)
13 t_{d(ACLKRX-AFSRX)}
14 t_{d(ACLKX-AXRV)}
15 t_{dis(ACLKX-AXRHZ)}
PARAMETER
Cycle time, AHCLKR/X
Pulse duration, AHCLKR/X high or low
Cycle time, ACLKR/X
ACLKR/X int
Pulse duration, ACLKR/X high or low ACLKR/X int
Delay time, ACLKR/X transmit edge
to AFSX/R output valid⁽⁶⁾
ACLKR/X int
ACLKR/X ext input
ACLKR/X ext output
Delay time, ACLKX transmit edge to
AXR output valid
ACLKR/X int
ACLKR/X ext input
ACLKR/X ext output
Disable time, ACLKR/X transmit
edge to AXR high impedance
following last data bit
ACLKR/X int
ACLKR/X ext
1.3V, 1.2V
MIN
MAX
25
AH – 2.5⁽²⁾
25 ^{(3) (4)}
A – 2.5⁽⁵⁾
-1
6
2
13.5
2
13.5
-1
6
2
13.5
2
13.5
0
6
2
13.5
1.1V
MIN
28
AH – 2.5⁽²⁾
28^{(3) (4)}
A – 2.5⁽⁵⁾
-1
2
2
-1
2
2
0
MAX
8
14.5
14.5
8
15
15
8
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2
15 ns
(1) McASP0 ACLKX0 internal – ACLKXCTL.CLKXM = 1, PDIR.ACLKX = 1
ACLKX0 external input – McASP0 ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 0
ACLKX0 external output – McASP0ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 1
ACLKR0 internal – McASP0 ACLKR0CTL.CLKRM = 1, PDIR.ACLKR =1
ACLKR0 external input – McASP0 ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 0
ACLKR0 external output – McASP0 ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 1
(2) AH = (AHCLKR/X period)/2 in ns. For example, when AHCLKR/X period is 25 ns, use AH = 12.5 ns.
(3) P = SYSCLK2 period
(4) This timing is limited by the timing shown or 2P, whichever is greater.
(5) A = (ACLKR/X period)/2 in ns. For example, when AHCLKR/X period is 25 ns, use AH = 12.5 ns.
(6) McASP0 ACLKXCTL.ASYNC=1: Receiver is clocked by its own ACLKR0
Table 5-55. Switching Characteristics for McASP0 (1.0V)⁽¹⁾
NO.
PARAMETER
9 t_c(AHCLKRX)
10 t_w(AHCLKRX)
11 t_c(ACLKRX)
12 t_w(ACLKRX)
Cycle time, AHCLKR/X
Pulse duration, AHCLKR/X high or low
Cycle time, ACLKR/X
Pulse duration, ACLKR/X high or low
13 t_{d(ACLKRX-AFSRX)}
Delay time, ACLKR/X transmit edge to AFSX/R output
valid ⁽⁶⁾
ACLKR/X int
ACLKR/X int
ACLKR/X int
ACLKR/X ext input
ACLKR/X ext output
ACLKR/X int
14 t_{d(ACLKX-AXRV)}
Delay time, ACLKX transmit edge to AXR output valid
ACLKR/X ext input
ACLKR/X ext output
15 t_{dis(ACLKX-AXRHZ)}
Disable time, ACLKR/X transmit edge to AXR high
impedance following last data bit
ACLKR/X int
ACLKR/X ext
(1) McASP0 ACLKX0 internal – ACLKXCTL.CLKXM = 1, PDIR.ACLKX = 1
ACLKX0 external input – McASP0 ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 0
ACLKX0 external output – McASP0ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 1
ACLKR0 internal – McASP0 ACLKR0CTL.CLKRM = 1, PDIR.ACLKR =1
ACLKR0 external input – McASP0 ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 0
ACLKR0 external output – McASP0 ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 1
(2) AH = (AHCLKR/X period)/2 in ns. For example, when AHCLKR/X period is 25 ns, use AH = 12.5 ns.
(3) P = SYSCLK2 period
(4) This timing is limited by the timing shown or 2P, whichever is greater.
(5) A = (ACLKR/X period)/2 in ns. For example, when AHCLKR/X period is 25 ns, use AH = 12.5 ns.
(6) McASP0 ACLKXCTL.ASYNC=1: Receiver is clocked by its own ACLKR0
1.0V
MIN
35
AH – 2.5⁽²⁾
35 ^{(3) (4)}
A – 2.5⁽⁵⁾
-0.5
2
2
-0.5
2
2
0
2
MAX
10
19
19
10
19
19
10
19
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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Peripheral Information and Electrical Specifications 137
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