AM1808_11 Datasheet, PDF (24/262 Pages) Texas Instruments – AM1808 ARM Microprocessor

AM1808
SPRS653C – FEBRUARY 2010 – REVISED DECEMBER 2011
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Table 2-8. DDR2 Controller (DDR2) Terminal Functions (continued)
DDR_DQS[0]
DDR_DQS[1]
DDR_BA[2]
DDR_BA[1]
DDR_BA[0]
SIGNAL
NAME
DDR_DQGATE0
DDR_DQGATE1
DDR_ZP
DDR_VREF
DDR_DVDD18
TYPE ⁽¹⁾
NO.
T14
I/O
V11
I/O
U8
O
T9
O
V8
O
R11
O
R12
I
U12
O
R6
I
N10, P10, N9,
P9, R9, P8,
R8, P7, R7,
N6
PWR
PULL ⁽²⁾
DESCRIPTION
IPD
DDR2 data strobe inputs/outputs
IPD
IPD
IPD DDR2 SDRAM bank address
IPD
DDR2 loopback signal for external DQS gating.
IPD Route to DDR and back to DDR_DQGATE1 with
same constraints as used for DDR clock and data.
DDR2 loopback signal for external DQS gating.
IPD Route to DDR and back to DDR_DQGATE0 with
same constraints as used for DDR clock and data.
DDR2 reference output for drive strength calibration
—
of N and P channel outputs. Tie to ground via 50
ohm resistor @ 5% tolerance.
DDR voltage input for the DDR2/mDDR I/O buffers.
—
Note even in the case of mDDR an external resistor
divider connected to this pin is necessary.
—
DDR PHY 1.8V power supply pins
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