AM1808_11 Datasheet, PDF (41/262 Pages) Texas Instruments – AM1808 ARM Microprocessor

AM1808
www.ti.com
SPRS653C – FEBRUARY 2010 – REVISED DECEMBER 2011
2.7.19 Multimedia Card/Secure Digital (MMC/SD)
Table 2-21. Multimedia Card/Secure Digital (MMC/SD) Terminal Functions
SIGNAL
NAME
TYPE ⁽¹⁾
NO.
PULL ⁽²⁾
POWER
GROUP ⁽³⁾
DESCRIPTION
MMCSD0
MMCSD0_CLK / PRU1_R30[31] / GP4[7]
E9
O
CP[18]
B
MMCSD0 Clock
EMA_A[22] / MMCSD0_CMD / PRU1_R30[30] / GP4[6]
A10
I/O
CP[18]
B
MMCSD0 Command
EMA_A[14] / MMCSD0_DAT[7] / PRU1_R30[22] / GP5[14] /
PRU1_R31[22]
A12
I/O
CP[19]
B
EMA_A[15] / MMCSD0_DAT[6] / PRU1_R30[23] / GP5[15] /
PRU1_R31[23]
C11 I/O
CP[19]
B
EMA_A[16] / MMCSD0_DAT[5] / PRU1_R30[24] / GP4[0]
EMA_A[17] / MMCSD0_DAT[4] / PRU1_R30[25] / GP4[1]
E12
I/O
B11
I/O
CP[18]
CP[18]
B
B
MMC/SD0 data
EMA_A[18] / MMCSD0_DAT[3] / PRU1_R30[26] / GP4[2]
E11
I/O
CP[18]
B
EMA_A[19] / MMCSD0_DAT[2] / PRU1_R30[27] / GP4[3]
C10 I/O
CP[18]
B
EMA_A[20] / MMCSD0_DAT[1] / PRU1_R30[28] / GP4[4]
A11
I/O
CP[18]
B
EMA_A[21] / MMCSD0_DAT[0] / PRU1_R30[29] / GP4[5]
B10
I/O
CP[18]
B
MMCSD1
PRU0_R30[24] /MMCSD1_CLK / UPP_CHB_START /
GP8[14]/PRU1_R31[26]/
G2
O
CP[30]
C
MMCSD1 Clock
PRU0_R30[23] /MMCSD1_CMD / UPP_CHB_ENABLE /
GP8[13]/PRU1_R31[25]
J4
I/O
CP[30]
C
MMCSD1 Command
MMCSD1_DAT[7] / LCD_PCLK / PRU1_R30[7] / GP8[11]
F1
I/O
CP[31]
C
MMCSD1_DAT[6] / LCD_MCLK /PRU1_R30[6] / GP8[10] /
PRU1_R31[7]
F2
I/O
CP[31]
C
MMCSD1_DAT[5] / LCD_HSYNC /PRU1_R30[5] / GP8[9] /
PRU1_R31[6]
H4
I/O
CP[31]
C
MMCSD1_DAT[4] / LCD_VSYNC /PRU1_R30[4] / GP8[8] /
PRU1_R31[5]
VP_CLKIN2 / MMCSD1_DAT[3] / PRU1_R30[3] / GP6[4] /
PRU1_R31[4]
G4
I/O
H3
I/O
CP[31]
CP[30]
C
MMC/SD1 data
C
VP_CLKOUT2 / MMCSD1_DAT[2] / PRU1_R30[2] / GP6[3] /
PRU1_R31[3]
K3
I/O
CP[30]
C
VP_CLKIN3 / MMCSD1_DAT[1]/ PRU1_R30[1] / GP6[2] /
PRU1_R31[2]
J3
I/O
CP[30]
C
PRU0_R30[25] / MMCSD1_DAT[0] / UPP_CHB_CLOCK / GP8[15]/
PRU1_R31[27]
G1
I/O
CP[30]
C
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the signal name
highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured
function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different
types (ie., input versus output), the table reflects the pin function direction for that particular peripheral.
(2) IPD = Internal Pulldown resistor; IPU = Internal Pullup resistor; CP[n] = configurable pull-up/pull-down (where n is the pin group) using
the PUPDENA and PUPDSEL registers in the System Module. The pull-up and pull-down control of these pins is not active until the
device is out of reset. During reset, all of the pins associated with these registers are pulled down. If the application requires a pull-up,
an external pull-up can be used. For electrical specifications on the pull-up and and internal pull-down circuits, see the Device Operating
Conditions section.
(3) This signal is part of a dual-voltage IO group (A, B or C). These groups can be operated at 3.3V or 1.8V nominal. The three groups can
be operated at independent voltages but all pins withina group will operate at the same voltage. Group A operates at the voltage of
power supply DVDD3318_A. Group B operates at the voltage of power supply DVDD3318_B. Group C operates at the voltage of power
supply DVDD3318_C.
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