TMS320DM6435 Datasheet, PDF (90/252 Pages) Texas Instruments – Digital Media Processor

TMS320DM6435
Digital Media Processor
SPRS344B – NOVEMBER 2006 – REVISED NOVEMBER 2007
www.ti.com
3.7.1 Pin Muxing Selection At Reset
This section summarizes pin mux selection at reset.
The configuration pins AEM[2:0] and AEAW[2:0] latched at device reset determine default pin muxing for
the following Pin Mux Blocks:
• EMIFA/VPSS Block: default pin mux determined by AEM[2:0] and AEAW[2:0]. After reset, software
may modify settings in the PINMUX0 register to add VPFE functionalities into this block.
– AEM[2:0] = 000b, AEAW[2:0] = don't care: Major Config Option A is selected. This block defaults to
61 GPIO pins.
– AEM[2:0] = 001b, AEAW[2:0] = 000b to 100b: Major Config Option B is selected. This block
defaults to 8-bit EMIFA (Async) Pinout Mode 1, plus 24-to-32 GPIO pins.
– AEM[2:0] = 101b, AEAW[2:0] = don't care: Major Config Option E is selected. This block defaults to
8-bit EMIFA (NAND) Pinout mode 5, plus 47 GPIO pins.
For a description of the PINMUX0 and PINMUX1 registers and more details on pin muxing, see
Section 3.7.2, Pin Muxing Selection After Reset.
3.7.2 Pin Muxing Selection After Reset
The PINMUX0 and PINMUX1 registers in the System Module allow software to select the pin functions in
the Pin Mux Blocks. The pin control of some of the Pin Mux Blocks requires a combination of
PINMUX0/PINMUX1 bit fields. For more details on the combination of the PINMUX bit fields that control
each muxed pin, see Section 3.7.3.1, Multiplexed Pins on DM6435.
This section only provides an overview of the PINMUX0 and PINMUX1 registers. For more detailed
discussion on how to program each Pin Mux Block, see Section 3.7.3, Pin Multiplexing Details.
3.7.2.1 PINMUX0 Register Description
The Pin Multiplexing 0 Register (PINMUX0) controls the pin function in the EMIFA/VPSS Block. The
PINMUX0 register format is shown in Figure 3-12 and the bit field descriptions are given in Table 3-19.
Some muxed pins are controlled by more than one PINMUX bit field. For the combination of the PINMUX
bit fields that control each muxed pin, see Section 3.7.3.1, Multiplexed Pins on DM6435. For more
information on EMIFA/VPSS Block pin muxing, see Section 3.7.3.11, EMIFA/VPSS Block Muxing. For the
pin-by-pin muxing control of the EMIFA/VPSS Block, see Section 3.7.3.11.7, EMIFA/VPSS Block
Pin-By-Pin Multiplexing Summary.
31
30
29
28
27
26
25
24
23
22
21
20
19
RSV
CI10SEL
RSV
CI32SEL
RSV
CI54SEL CI76SEL CFLDSEL
CWEN
SEL
HVDSEL
RSV CCDCSEL RSV
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
18
17
16
AEAW
R/W-LLL
15
14
13
12
11
10
9
8
7
6
5
4
3
RESERVED
CS3SEL
CS4SEL
CS5SEL
RESERVED
R/W-0000
R/W-00
R/W-00
R/W-00
R/W-000
LEGEND: R/W = Read/Write; R = Read only; L = pin state latched at reset rising edge; -n = value after reset
(1) _{For proper DM6435 device operation, always write a value of "0" to all RESERVED/RSV bits.}
Figure 3-12. PINMUX0 Register— 0x01C4 0000 ⁽¹⁾
2
1
0
AEM
R/W-LLL
90
Device Configuration
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