TMS320DM6435 Datasheet, PDF (53/252 Pages) Texas Instruments – Digital Media Processor

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TMS320DM6435
Digital Media Processor
SPRS344B – NOVEMBER 2006 – REVISED NOVEMBER 2007
Table 2-22. PWM0, PWM1, and PWM2 Terminal Functions
SIGNAL
NAME
ZWT
NO.
CLKOUT0/PWM2/
GP[84]
M1
GP[4]/PWM1
F3
URTS0/PWM0/
GP[88]
L3
ZDU
NO.
R1
F3
M3
TYPE ⁽¹⁾
I/O/Z
I/O/Z
I/O/Z
OTHER ^{(2) (3)}
DESCRIPTION
IPD
DV_DD33
IPD
DV_DD33
IPU
DV_DD33
PWM2
This pin is multiplexed between the System Clock generator (PLL1),
PWM2, and GPIO.
For PWM2, this pin is output PWM2.
PWM1
This pin is multiplexed between GPIO and PWM1.
For PWM1, this pin is output PWM1.
PWM0
This pin is multiplexed between the UART0 (Flow Control), PWM0,
and GPIO.
For PWM0, this pin is output PWM0.
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
(2) IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external
pullup/pulldown resistors are required, see Section 3.9.1, Pullup/Pulldown Resistors.
(3) Specifies the operating I/O supply voltage for each signal
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