TMS320DM6435 Datasheet, PDF (41/252 Pages) Texas Instruments – Digital Media Processor

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TMS320DM6435
Digital Media Processor
SPRS344B – NOVEMBER 2006 – REVISED NOVEMBER 2007
Table 2-13. EMAC and MDIO Terminal Functions
SIGNAL
NAME
ZWT
NO.
ZDU
NO.
TYPE ⁽¹⁾
OTHER ^{(2) (3)}
DESCRIPTION
EMAC
HCNTL1/MTXEN/
GP[75]
D3
C4
I/O/Z
IPD
DV_DD33
This pin is multiplexed between HPI, Ethernet MAC (EMAC), and
GPIO.
In Ethernet MAC mode, it is Transmit Enable output MTXEN.
HD15/MTXCLK/
GP[73]
A4
A4
I/O/Z
IPD
DV_DD33
This pin is multiplexed between HPI, Ethernet MAC (EMAC), and
GPIO.
In Ethernet MAC mode, it is Transmit Clock input MTXCLK.
HD9/MCOL/
GP[67]
C6
C6
I/O/Z
IPD
DV_DD33
This pin is multiplexed between HPI, Ethernet MAC (EMAC), and
GPIO.
In Ethernet MAC mode, it is Collision Detect input MCOL.
HD11/MTXD3/
GP[69]
C5
A5
I/O/Z
IPD
DV_DD33
This pin is multiplexed between HPI, Ethernet MAC (EMAC), and
GPIO.
In Ethernet MAC mode, it is Transmit Data 3 output MTXD3.
HD12/MTXD2/
GP[70]
D5
C5
I/O/Z
IPD
DV_DD33
This pin is multiplexed between HPI, Ethernet MAC (EMAC), and
GPIO.
In Ethernet MAC mode, it is Transmit Data 2 output MTXD2.
HD13/MTXD1/
GP[71]
B4
B4
I/O/Z
IPD
DV_DD33
This pin is multiplexed between HPI, Ethernet MAC (EMAC), and
GPIO.
In Ethernet MAC mode, it is Transmit Data 1 output MTXD1.
HD14/MTXD0/
GP[72]
D4
B5
I/O/Z
IPD
DV_DD33
This pin is multiplexed between HPI, Ethernet MAC (EMAC), and
GPIO.
In Ethernet MAC mode, it is Transmit Data 0 output MTXD0.
HR/W/MRXCLK/
GP[77]
A3
A3
I/O/Z
IPD
DV_DD33
This pin is multiplexed between HPI, Ethernet MAC (EMAC), and
GPIO.
In Ethernet MAC mode, it is Receive Clock input MRXCLK.
HHWIL/MRXDV/
GP[74]
C4
D3
I/O/Z
IPD
DV_DD33
This pin is multiplexed between HPI, Ethernet MAC (EMAC), and
GPIO.
In Ethernet MAC mode, it is Receive Data Valid input MRXDV.
HCNTL0/MRXER/
GP[76]
B3
B2
I/O/Z
IPD
DV_DD33
This pin is multiplexed between HPI, Ethernet MAC (EMAC), and
GPIO.
In Ethernet MAC mode, it is Receive Error input MRXER.
HD10/MCRS/
GP[68]
B5
B6
I/O/Z
IPD
DV_DD33
This pin is multiplexed between HPI, Ethernet MAC (EMAC), and
GPIO.
In Ethernet MAC mode, it is Carrier Sense input MCRS.
HINT/MRXD3/
GP[82]
C2
D2
I/O/Z
IPU
DV_DD33
This pin is multiplexed between HPI, Ethernet MAC (EMAC), and
GPIO.
In Ethernet MAC mode, it is Receive Data 3 input MRXD3.
HRDY/MRXD2/
GP[80]
D2
C3
I/O/Z
IPU
DV_DD33
This pin is multiplexed between HPI, Ethernet MAC (EMAC), and
GPIO.
In Ethernet MAC mode, it is Receive Data 2 input MRXD2.
HDS1/MRXD1/
GP[79]
B2
B3
I/O/Z
IPU
DV_DD33
This pin is multiplexed between HPI, Ethernet MAC (EMAC), and
GPIO.
In Ethernet MAC mode, it is Receive data 1 input MRXD1.
HDS2/MRXD0/
GP[78]
C3
C2
I/O/Z
IPU
DV_DD33
This pin is multiplexed between HPI, Ethernet MAC (EMAC), and
GPIO.
In Ethernet MAC mode, it is Receive Data 0 input MRXD0.
MDIO
HCS/MDCLK/
GP[81]
C1
D1
I/O/Z
IPU
DV_DD33
This pin is multiplexed between HPI, MDIO, and GPIO.
In Ethernet MAC mode, it is Management Data Clock output
MDCLK.
HAS/MDIO/
GP[83]
D1
C1
I/O/Z
IPU
DV_DD33
This pin is multiplexed between HPI, MDIO, and GPIO.
In Ethernet MAC mode, it is Management Data IO MDIO (I/O/Z).
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
(2) IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external
pullup/pulldown resistors are required, see Section 3.9.1, Pullup/Pulldown Resistors.
(3) Specifies the operating I/O supply voltage for each signal
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