TMS320DM6435 Datasheet, PDF (146/252 Pages) Texas Instruments – Digital Media Processor

TMS320DM6435
Digital Media Processor
SPRS344B – NOVEMBER 2006 – REVISED NOVEMBER 2007
Table 6-7. DM6435 EDMA Registers (continued)
HEX ADDRESS
0x01C0 2208
0x01C0 220C
0x01C0 2210
0x01C0 2214
0x01C0 2218
0x01C0 221C
0x01C0 2220
0x01C0 2224
0x01C0 2228
0x01C0 222C
0x01C0 2230
0x01C0 2234
0x01C0 2238
0x01C0 223C
0x01C0 2240
0x01C0 2244
0x01C0 2248 - 0x01C0 224C
0x01C0 2250
0x01C0 2254
0x01C0 2258
0x01C0 225C
0x01C0 2260
0x01C0 2264
0x01C0 2268
0x01C0 226C
0x01C0 2270
0x01C0 2274
0x01C0 2278
0x01C0 227C
0x01C0 2280
0x01C0 2284
0x01C0 2288
0x01C0 228C
0x01C0 2290
0x01C0 2294
0x01C0 2298 - 0x01C0 23FC
0x01C0 2400 - 0x01C0 25FC
0x01C0 2600 - 0x01C0 27FC
0x01C0 2800 - 0x01C0 29FC
0x01C0 2A00 - 0x01C0 2BFC
0x01C0 2C00 - 0x01C0 2DFC
0x01C0 2E00 - 0x01C0 2FFC
0x01C0 2FFD - 0x01C0 3FFF
0x01C0 4000 - 0x01C0 4FFF
0x01C0 5000 - 0x01C0 7FFF
0x01C0 8000 - 0x01C0 FFFF
ACRONYM
REGISTER NAME
ECR
Event Clear Register
ECRH
Event Clear Register High
ESR
Event Set Register
ESRH
Event Set Register High
CER
Chained Event Register
CERH
Chained Event Register High
EER
Event Enable Register
EERH
Event Enable Register High
EECR
Event Enable Clear Register
EECRH
Event Enable Clear Register High
EESR
Event Enable Set Register
EESRH
Event Enable Set Register High
SER
Secondary Event Register
SERH
Secondary Event Register High
SECR
Secondary Event Clear Register
SECRH
Secondary Event Clear Register High
-
Reserved
IER
Interrupt Enable Register
IERH
Interrupt Enable Register High
IECR
Interrupt Enable Clear Register
IECRH
Interrupt Enable Clear Register High
IESR
Interrupt Enable Set Register
IESRH
Interrupt Enable Set Register High
IPR
Interrupt Pending Register
IPRH
Interrupt Pending Register High
ICR
Interrupt Clear Register
ICRH
Interrupt Clear Register High
IEVAL
Interrupt Evaluate Register
-
Reserved
QER
QDMA Event Register
QEER
QDMA Event Enable Register
QEECR
QDMA Event Enable Clear Register
QEESR
QDMA Event Enable Set Register
QSER
QDMA Secondary Event Register
QSECR
QDMA Secondary Event Clear Register
-
Reserved
-
Reserved
-
Reserved
-
Reserved
-
Reserved
-
Reserved
-
Reserved
-
Reserved
-
Parameter Set RAM (see Table 6-8)
-
Reserved
-
Reserved
Transfer Controller 0 Registers
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