TMS320DM6435 Datasheet, PDF (167/252 Pages) Texas Instruments – Digital Media Processor

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TMS320DM6435
Digital Media Processor
SPRS344B – NOVEMBER 2006 – REVISED NOVEMBER 2007
6.7.4 Clock PLL Electrical Data/Timing (Input and Output Clocks)
Table 6-19. Timing Requirements for MXI/CLKIN (-4 -4Q,-4S,-5,-5Q,-5S,-6) Devices^(1)(2)(3)(4) (see
Figure 6-12)
NO.
1
t_c(MXI)
2
t_w(MXIH)
3
t_w(MXIL)
4
t_t(MXI)
5
t_J(MXI)
Cycle time, MXI/CLKIN
Pulse duration, MXI/CLKIN high
Pulse duration, MXI/CLKIN low
Transition time, MXI/CLKIN
Period jitter, MXI/CLKIN
Frequency Stability
-4/-4Q/-4S
-5/-5Q/-5S
-6
MIN
MAX
33.3
50
0.45C
0.55C
0.45C
0.55C
0.05C
0.02C
±50
UNIT
ns
ns
ns
ns
ns
ppm
(1) The MXI/CLKIN frequency and PLL multiply factor should be chosen such that the resulting clock frequency is within the specific range
for CPU operating frequency. For example, for a -6 speed device with a 27 MHz CLKIN frequency, the PLL multiply factor should be
≤ 22.
(2) The reference points for the rise and fall transitions are measured at V_IL MAX and V_IH MIN.
(3) For more details on the PLL multiplier factors, see the TMS320DM63x DMP DSP Subsystem Reference Guide (literature number
SPRU978).
(4) C = CLKIN cycle time in ns. For example, when MXI/CLKIN frequency is 27 MHz, use C = 37.037 ns.
5
1
4
2
MXI/CLKIN
3
4
Figure 6-12. MXI/CLKIN Timing
Table 6-20. Switching Characteristics Over Recommended Operating Conditions for CLKOUT0⁽¹⁾⁽²⁾
(see Figure 6-13)
NO.
PARAMETER
-4/-4Q/-4S
-5/-5Q/-5S
-6
UNIT
MIN
MAX
1 t_C
2 t_w(CLKOUT0H)
3 t_w(CLKOUT0L)
4 t_t(CLKOUT0)
Cycle time, CLKOUT0
Pulse duration, CLKOUT0 high
Pulse duration, CLKOUT0 low
Transition time, CLKOUT0
33.3
0.45P
0.45P
50 ns
0.55P ns
0.55P ns
0.05P ns
(1) The reference points for the rise and fall transitions are measured at V_OL MAX and V_OH MIN.
(2) P = 1/CLKOUT0 clock frequency in nanoseconds (ns). For example, when CLKOUT0 frequency is 27 MHz, use P = 37.04 ns.
2
1
4
CLK_OUT0
(Divide-by-1)
3
4
Figure 6-13. CLKOUT0 Timing
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Peripheral Information and Electrical Specifications 167