CD74HC4046A Datasheet, PDF (9/28 Pages) Texas Instruments – High-Speed CMOS Logic Phase-Locked Loop with VCO

CD54HC4046A, CD74HC4046A, CD54HCT4046A, CD74HCT4046A
DC Electrical Specifications (Continued)
PARAMETER
SIG_IN, COMP_IN
DC Coupled
Low-Level Input
Voltage
SYMBOL
V_IL
TEST
CONDITIONS
V_I (V)
-
I_O (mA)
-
V_CC
(V)
4.5 to
5.5
25^oC
-40^oC TO 85^oC -55^oC TO 125^oC
MIN TYP MAX MIN MAX MIN MAX UNITS
-
-
0.8
-
0.8
-
0.8
V
PCP_OUT, PCn OUT
V_OH V_IL or V_IH
-
4.5
4.4
-
-
4.4
-
4.4
-
V
High-Level Output
Voltage
CMOS Loads
PCP_OUT, PCn OUT
V_OH V_IL or V_IH
-
4.5
3.98
-
-
3.84
-
3.7
-
V
High-Level Output
Voltage
TTL Loads
PCP_OUT, PCn OUT
Low-Level Output
Voltage
CMOS Loads
V_OL V_IL or V_IH
-
4.5
-
-
0.1
-
0.1
-
0.1
V
PCP_OUT, PCn OUT
Low-Level Output
Voltage
TTL Loads
V_OL V_IL or V_IH
-
4.5
-
-
0.26
-
0.33
-
0.4
V
SIG_IN, COMP_IN Input
I_I
Any
-
5.5
-
-
±30
±38
Leakage Current
Voltage
Between
V_CC and
GND
±45
µA
PC2_OUT Three-State
I_OZ V_IL or V_IH
-
Off-State Current
5.5
-
-
±0.5 ±5
-
-
±10
µA
SIG_IN, COMP_IN Input
R_I
V_I at Self-Bias
4.5
-
250
-
-
-
-
-
kΩ
Resistance
Operation Point:
∆V_I = 0.5V,
See Figure 10
DEMODULATOR SECTION
Resistor Range
R_S
at R_S > 300kΩ
4.5
5
-
300
-
-
-
-
kΩ
Leakage Current
Can Influence
V_{DEM OUT}
Offset Voltage VCO_IN V_OFF
V_I = V_{VCO IN} =
4.5
-
±20
-
-
-
-
-
mV
to V_DEM
V_CC
2
Values taken over
R_S Range
See Figure 23
Dynamic Output
Resistance at
DEM_OUT
Quiescent Device
Current
R_D
V_{DEM OUT} =
V_CC
2
I_CC
V_CC or
-
GND
4.5
-
25
-
5.5
-
-
8
-
-
-
80
-
-
Ω
-
160
µA
Additional Quiescent
∆I_CC
V_CC
Device Current Per (Note 4) -2.1
-
4.5 to
-
100 360
-
450
-
490
µA
5.5
Input Pin: 1 Unit Load
Excluding
Pin 5
NOTES:
2. The value for R1 and R2 in parallel should exceed 2.7kΩ.
3. The maximum operating voltage can be as high as V_CC -0.9V, however, this may result in an increased offset voltage.
4. For dual-supply systems theoretical worst case (V_I = 2.4V, V_CC = 5.5V) specification is 1.8mA.
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