CD74HC4046A Datasheet, PDF (20/28 Pages) Texas Instruments – High-Speed CMOS Logic Phase-Locked Loop with VCO

CD54HC4046A, CD74HC4046A, CD54HCT4046A, CD74HCT4046A
SUBJECT
PLL Conditions with
No Signal at the
SIG_IN Input
PLL Frequency
Capture Range
PHASE
COMPARATOR
PC1
PC2
PC3
PC1, PC2 or PC3
DESIGN CONSIDERATIONS
VCO adjusts to f_o with φ_DEMOUT = 90^o and V_VCOIN = 1/2 V_CC (see Figure 2)
VCO adjusts to f_MIN with φ_DEMOUT = -360^o and V_VCOIN = 0V (see Figure 4)
VCO adjusts to f_MAX with φ_DEMOUT = 360^o and V_VCOIN = V_CC (see Figure 6)
Loop Filter Component Selection
R3
|F_(jω)|
INPUT ^C2 OUTPUT
-1/_τ
ω
(A) τ = R3 x C2
(B) AMPLITUDE CHARACTERISTIC (C) POLE-ZERO DIAGRAM
A small capture range (2f_c) is obtained if τ > 2f_c ≈ 1/π (2πf_L/τ.)^1/2
FIGURE 46. SIMPLE LOOP FILTER FOR PLL WITHOUT OFFSET
PLL Locks on
Harmonics at Center
Frequency
Noise Rejection at
Signal Input
AC Ripple Content
when PLL is Locked
PC1 or PC3
PC2
PC1
PC2 or PC3
PC1
PC2
PC3
R3
R4
INPUT
C2
|F_(jω)|
OUTPUT
m
m = ^R4
R3 + R4
-1/_τ2 -1/_τ3
(A) τ1 = R3 x C2;
τ2 = R4 x C2;
τ3 = (R3 + R4) x C2
1/_τ3 1/_τ2 ω
(B) AMPLITUDE CHARACTERISTIC
(C) POLE-ZERO DIAGRAM
FIGURE 47. SIMPLE LOOP FILTER FOR PLL WITH OFFSET
Yes
No
High
Low
f_r = 2f_i, large ripple content at φ_DEMOUT = 90^o
f_r = f_i, small ripple content at φ_DEMOUT = 0^o
f_r = fSIG_IN, large ripple content at φ_DEMOUT = 180^o
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