CD74HC4046A Datasheet, PDF (3/28 Pages) Texas Instruments – High-Speed CMOS Logic Phase-Locked Loop with VCO

CD54HC4046A, CD74HC4046A, CD54HCT4046A, CD74HCT4046A
C1
6
74
C1_A C1_B
3
14
COMP_IN SIG_IN
PC1_{OUT 2}
12 ^R2
R2
11 ^R1
R1
V_REF
-
VCO
-₊
10
R5
DEM_OUT
-₊
S_D
Q
Q
R_D
D ^{Q UP}
CP Q
R_D
INH
VCO_IN
5
9
V_CC
Q
D
CP _Q ^DOWN
R_D
FIGURE 1. LOGIC DIAGRAM
PC3_{OUT 15}
V_CC
p
PC2_OUT
13
n
GND
1
PCP_OUT
R3
C2
General Description
VCO
The VCO requires one external capacitor C1 (between C1_A
and C1_B) and one external resistor R1 (between R₁ and
GND) or two external resistors R1 and R2 (between R₁ and
GND, and R₂ and GND). Resistor R1 and capacitor C1
determine the frequency range of the VCO. Resistor R2
enables the VCO to have a frequency offset if required. See
logic diagram, Figure 1.
The high input impedance of the VCO simplifies the design
of low-pass filters by giving the designer a wide choice of
resistor/capacitor ranges. In order not to load the low-pass
filter, a demodulator output of the VCO input voltage is
provided at pin 10 (DEM_OUT). In contrast to conventional
techniques where the DEM_OUT voltage is one threshold
voltage lower than the VCO input voltage, here the DEM_OUT
voltage equals that of the VCO input. If DEM_OUT is used, a
load resistor (R_S) should be connected from DEM_OUT to
GND; if unused, DEM_OUT should be left open. The VCO
output (VCO_OUT) can be connected directly to the
comparator input (COMP_IN), or connected via a frequency-
divider. The VCO output signal has a specified duty factor of
50%. A LOW level at the inhibit input (INH) enables the VCO
and demodulator, while a HIGH level turns both off to
minimize standby power consumption.
Phase Comparators
The signal input (SIG_IN) can be directly coupled to the self-
biasing amplifier at pin 14, provided that the signal swing is
between the standard HC family input logic levels.
Capacitive coupling is required for signals with smaller
swings.
Phase Comparator 1 (PC1)
This is an Exclusive-OR network. The signal and comparator
input frequencies (f_i) must have a 50% duty factor to obtain
the maximum locking range. The transfer characteristic of
PC1, assuming ripple (f_r = 2f_i) is suppressed, is:
V_DEMOUT = (V_CC/π) (φSIG_IN - φCOMP_IN) where V_DEMOUT
is the demodulator output at pin 10; V_DEMOUT = V_PC1OUT
(via low-pass filter).
The average output voltage from PC1, fed to the VCO input
via the low-pass filter and seen at the demodulator output at
pin 10 (V_DEMOUT), is the resultant of the phase differences
of signals (SIG_IN) and the comparator input (COMP_IN) as
shown in Figure 2. The average of V_DEM is equal to 1/2
V_CC when there is no signal or noise at SIG_IN, and with this
input the VCO oscillates at the center frequency (f_o).
Typical waveforms for the PC1 loop locked at f_o are shown
in Figure 3.
3