CD74HC4046A Datasheet, PDF (10/28 Pages) Texas Instruments – High-Speed CMOS Logic Phase-Locked Loop with VCO

CD54HC4046A, CD74HC4046A, CD54HCT4046A, CD74HCT4046A
HCT Input Loading Table
INPUT
UNIT LOADS
INH
1
NTaObTleE, :e.Ugn.,it3l6o0a_µdAism∆_{aICxC. alitm2i5t o}sCpe. cific in DC Electrical Specifications
Switching Specifications C_L = 50pF, Input t_r, t_f = 6ns
PARAMETER
TEST
25^oC
-40^oC TO
85^oC
SYMBOL CONDITIONS V_CC (V) MIN TYP MAX MIN MAX
HC TYPES
PHASE COMPARATOR SECTION
Propagation Delay
t_PLH, t_PHL
SIG_IN, COMP_IN to PCI_OUT
2
-
- 200 - 250
4.5
-
-
40
-
50
6
-
-
34
-
43
SIG_IN, COMP_IN to PCP_OUT
2
-
- 300 - 375
4.5
-
-
60
-
75
6
-
-
51
-
64
SIG_IN, COMP_IN to PC3_OUT
2
-
- 245 - 305
4.5
-
-
49
-
61
6
-
-
42
-
52
Output Transition Time
t_THL, t_TLH
2
-
-
75
-
95
4.5
-
-
15
-
19
6
-
-
13
-
16
Output Enable Time, SIG_IN,
COMP_IN to PC2_OUT
t_PZH, t_PZL
2
-
- 265 - 330
4.5
-
-
53
-
66
6
-
-
45
-
56
Output Disable Time, SIG_IN,
COMP_IN to PC2_OUT
t_PHZ, t_PLZ
2
-
- 315 - 395
4.5
-
-
63
-
79
6
-
-
54
-
67
AC Coupled Input Sensitivity
(_P-P) at SIG_IN or COMP_IN
V_I(P-P)
3
-
11
-
-
-
4.5
-
15
-
-
-
6
-
33
-
-
-
VCO SECTION
Frequency Stability with
Temperature Change
∆f
∆T
R₁ =
R₂
100kΩ,
=∞
3
4.5
- 0.11 -
- 0.11 -
-
-
-
-
6
- 0.11 -
-
-
Maximum Frequency
f_MAX
C₁ = 50pF
3
-
24
-
-
-
R₁ =
R₂
3.5kΩ
=∞
4.5
-
24
-
-
-
6
-
24
-
-
-
C₁ = 0pF
3
-
38
-
-
-
R₁ =
R₂
9.1kΩ
=∞
4.5
-
38
-
-
-
6
-
38
-
-
-
-55^oC TO
125^oC
MIN MAX
-
300
-
60
-
51
-
450
-
90
-
77
-
307
-
74
-
63
-
110
-
22
-
19
-
400
-
80
-
68
-
475
-
95
-
81
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
mV
mV
mV
%/^oC
%/^oC
%/^oC
MHz
MHz
MHz
MHz
MHz
MHz
10