CD74HC4046A Datasheet, PDF (4/28 Pages) Texas Instruments – High-Speed CMOS Logic Phase-Locked Loop with VCO

CD54HC4046A, CD74HC4046A, CD54HCT4046A, CD74HCT4046A
The frequency capture range (2f_C) is defined as the
frequency range of input signals on which the PLL will lock if
it was initially out-of-lock. The frequency lock range (2f_L) is
defined as the frequency range of input signals on which the
loop will stay locked if it was initially in lock. The capture
range is smaller or equal to the lock range.
With PC1, the capture range depends on the low-pass filter
characteristics and can be made as large as the lock range.
This configuration retains lock behavior even with very noisy
input signals. Typical of this type of phase comparator is that
it can lock to input frequencies close to the harmonics of the
VCO center frequency.
V_CC
V_{DEMOUT (AV)}
V_DEMOUT = (V_CC/4π) (φSIG_IN - φCOMP_IN) where
V_DEMOUT is the demodulator output at pin 10;
V_DEMOUT = V_PC2OUT (via low-pass filter).
The average output voltage from PC2, fed to the VCO via the
low-pass filter and seen at the demodulator output at pin 10
(V_DEMOUT), is the resultant of the phase differences of
SIG_IN and COMP_IN as shown in Figure 4. Typical waveforms
for the PC2 loop locked at f_o are shown in Figure 5.
V_CC
V_{DEMOUT (AV)}
1/2 V_CC
1/2 V_CC
0
-360^o
0^o
φ_DEMOUT
360^o
0
0^o
90^o
φ_DEMOUT
180^o
FIGURE 2. PHASE COMPARATOR 1: AVERAGE OUTPUT
VOLTAGE vs INPUT PHASE DIFFERENCE:
V_DEMOUT = V_PC1OUT = (V_CC/π) (φSIG_IN -
φCOMP_IN); φ_DEMOUT = (φSIG_IN - φCOMP_IN)
SIG_IN
COMP_IN
VCO_OUT
PC1_OUT
VCO_IN
V_CC
GND
FIGURE 3. TYPICAL WAVEFORMS FOR PLL USING PHASE
COMPARATOR 1, LOOP LOCKED AT f_o
Phase Comparator 2 (PC2)
This is a positive edge-triggered phase and frequency
detector. When the PLL is using this comparator, the loop
is controlled by positive signal transitions and the duty
factors of SIG_IN and COMP_IN are not important. PC2
comprises two D-type flip-flops, control-gating and a three-
state output stage. The circuit functions as an up-down
counter (Figure 1) where SIG_IN causes an up-count and
COMP_IN a down-count. The transfer function of PC2,
assuming ripple (f_r = f_i) is suppressed, is:
FIGURE 4. PHASE COMPARATOR 2: AVERAGE OUTPUT
VOLTAGE vs INPUT PHASE DIFFERENCE:
V_DEMOUT = V_PC2OUT
= (V_CC/4π) (φSIG_IN - φCOMP_IN);
φ_DEMOUT = (φSIG_IN - φCOMP_IN)
SIG_IN
COMP_IN
VCO_OUT
PC2_OUT
VCO_IN
HIGH IMPEDANCE OFF - STATE
PCP_OUT
V_CC
GND
FIGURE 5. TYPICAL WAVEFORMS FOR PLL USING PHASE
COMPARATOR 2, LOOP LOCKED AT f_o
When the frequencies of SIG_IN and COMP_IN are equal but
the phase of SIG_IN leads that of COMP_IN, the p-type output
driver at PC2_OUT is held “ON” for a time corresponding to
the phase difference (φ_DEMOUT). When the phase of SIG_IN
lags that of COMP_IN, the n-type driver is held “ON”.
When the frequency of SIG_IN is higher than that of
COMP_IN, the p-type output driver is held “ON” for most of
the input signal cycle time, and for the remainder of the
cycle both n- and p-type drivers are “OFF” (three-state). If
the SIG_IN frequency is lower than the COMP_IN frequency,
then it is the n-type driver that is held “ON” for most of the
cycle. Subsequently, the voltage at the capacitor (C2) of
the low-pass filter connected to PC2_OUT varies until the
signal and comparator inputs are equal in both phase and
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