CD74HC4046A Datasheet, PDF (8/28 Pages) Texas Instruments – High-Speed CMOS Logic Phase-Locked Loop with VCO

CD54HC4046A, CD74HC4046A, CD54HCT4046A, CD74HCT4046A
DC Electrical Specifications (Continued)
TEST
CONDITIONS
PARAMETER
Offset Voltage VCO_IN
to V_DEM
SYMBOL V_I (V) I_O (mA)
V_OFF
V_I = V_{VCO IN} =
V_CC
2
Values Taken Over
R_S Range
See Figure 23
Dynamic Output
Resistance at
DEM_OUT
R_D
V_DEMOUT =
V_CC
2
Quiescent Device
Current
I_CC
Pins 3, 5 and 14
at V_CC Pin 9 at
GND, I₁ at Pins 3
and 14 to be
excluded
HCT TYPES
VCO SECTION
INH High Level Input
V_IH
-
-
Voltage
INH Low Level Input
V_IL
-
-
Voltage
VCO_OUT High Level
Output Voltage
CMOS Loads
V_OH V_IH or V_IL -0.02
VCO_OUT High Level
-4
Output Voltage
TTL Loads
VCO_OUT Low Level
Output Voltage
CMOS Loads
V_OL V_IH or V_IL 0.02
VCO_OUT Low Level
4
Output Voltage
TTL Loads
C1A, C1B Low Level
Output Voltage
V_OL V_IH or V_IL
4
(Test Purposes Only)
INH VCO_IN Input
Leakage Current
I_I
Any Voltage
Between V_CC and
GND
R1 Range (Note 2)
-
-
-
R2 Range (Note 2)
-
-
-
C1 Capacitance
Range
-
-
-
VCO_IN Operating
Voltage Range
-
Over the range
specified for R1 for
Linearity See Figure
10, and 34 - 37
(Note 3)
PHASE COMPARATOR SECTION
SIG_IN, COMP_IN
DC Coupled
High-Level Input
Voltage
V_IH
-
-
V_CC
(V)
3
4.5
6
3
4.5
6
6
4.5 to
5.5
4.5 to
5.5
4.5
4.5
4.5
4.5
4.5
5.5
4.5
4.5
4.5
4.5
4.5 to
5.5
25^oC
-40^oC TO 85^oC -55^oC TO 125^oC
MIN TYP MAX MIN MAX MIN MAX UNITS
-
±30
-
-
-
-
-
mV
-
±20
-
-
-
-
-
mV
-
±10
-
-
-
-
-
mV
-
25
-
-
-
-
-
Ω
-
25
-
-
-
-
-
Ω
-
25
-
-
-
-
-
Ω
-
-
8
-
80
-
160
µA
2
-
-
2
-
2
-
V
-
-
0.8
-
0.8
-
0.8
V
4.4
-
-
4.4
-
4.4
-
V
3.98
-
-
3.84
-
3.7
-
V
-
-
0.1
-
0.1
-
0.1
V
-
-
0.26
-
0.33
-
0.4
V
-
-
0.40
-
0.47
-
0.54
V
-
±0.1
-
±1
-
±1
µA
3
-
300
-
-
-
-
kΩ
3
-
300
-
-
-
-
kΩ
0
-
No
-
-
-
-
pF
Limit
1.1
-
3.2
-
-
-
-
V
2
-
-
2
-
2
-
V
8