CD74HC4046A Datasheet, PDF (5/28 Pages) Texas Instruments – High-Speed CMOS Logic Phase-Locked Loop with VCO

CD54HC4046A, CD74HC4046A, CD54HCT4046A, CD74HCT4046A
frequency. At this stable point the voltage on C2 remains
constant as the PC2 output is in three-state and the VCO
input at pin 9 is a high impedance. Also in this condition,
the signal at the phase comparator pulse output (PCP_OUT)
is a HIGH level and so can be used for indicating a locked
condition.
Thus, for PC2, no phase difference exists between SIG_IN
and COMP_IN over the full frequency range of the VCO.
Moreover, the power dissipation due to the low-pass filter is
reduced because both p- and n-type drivers are “OFF” for
most of the signal input cycle. It should be noted that the
PLL lock range for this type of phase comparator is equal to
the capture range and is independent of the low-pass filter.
With no signal present at SIG_IN, the VCO adjusts, via PC2,
to its lowest frequency.
Phase Comparator 3 (PC3)
This is a positive edge-triggered sequential phase
detector using an RS-type flip-flop. When the PLL is using
this comparator, the loop is controlled by positive signal
transitions and the duty factors of SIG_IN and COMP_IN are
not important. The transfer characteristic of PC3,
assuming ripple (f_r = f_i) is suppressed, is:
V_DEMOUT = (V_CC/2p) (fSIG_IN - fCOMP_IN) where
V_DEMOUT is the demodulator output at pin 10; V_DEMOUT
= V_PC3OUT (via low-pass filter).
The average output from PC3, fed to the VCO via the low-
pass filter and seen at the demodulator at pin 10
(V_DEMOUT), is the resultant of the phase differences of
SIG_IN and COMP_IN as shown in Figure 6. Typical
waveforms for the PC3 loop locked at f_o are shown in
Figure 7.
The phase-to-output response characteristic of PC3
(Figure 6) differs from that of PC2 in that the phase angle
abnedtweisen18S0IG^{o IN}at
and
the
COMP_IN varies between
center frequency. Also
0^o and 360^o
PC3 gives a
greater voltage swing than PC2 for input phase differences
but as aconsequence the ripple content of the VCO input
signal is higher. With no signal present at SIG_IN, the VCO
adjusts, via PC3, to its highest frequency.
The only difference between the HC and HCT versions is the
input level specification of the INH input. This input disables
the VCO section. The comparator’s sections are identical, so
that there is no difference in the SIG_IN (pin 14) or COMP_IN
(pin 3) inputs between the HC and the HCT versions.
V_CC
V_{DEMOUT (AV)}
1/2 V_CC
0
0^o
180^o φDEMOUT
360^o
FIGURE 6. PHASE COMPARATOR 3: AVERAGE OUTPUT
VOLTAGE vs INPUT PHASE DIFFERENCE:
V_DEMOUT = V_PC3OUT
= (V_CC/2π) (φSIG_IN - φCOMP_IN);
φ_DEMOUT = (φSIG_IN - φCOMP_IN)
SIG_IN
COMP_IN
VCO_OUT
PC3_OUT
VCO_IN
V_CC
GND
FIGURE 7. TYPICAL WAVEFORMS FOR PLL USING PHASE
COMPARATOR 3, LOOP LOCKED AT f_o
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