BQ2024 Datasheet, PDF (9/19 Pages) Texas Instruments – 1.5K-BIT SERIAL EPROM WITH SDQ INTERFACE

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bq2024
SLUS770 – MAY 2007
For both of these cases, the decision to continue programming is made entirely by the host, because the
bq2024 is not able to determine if the 8-bit CRC calculated by the host agrees with the 8-bit CRC calculated by
the bq2024.
Prior to programming, bits in the 1536-bit EPROM data field appear as logical 1s.
Selected
State
Write Memory
N
Command?
(0Fh)
Y
Bus Master Transmits Low Byte Address
(LSB First) AD0 to AD7
Selected
State
Bus Master Transmits High Byte Address
(LSB First) AD8 to AD15
bq2024
Loads Address Into Address Counter
bq2024 Transmits CRC of Write Command
and Address, then Clears CRC Register
bq2024 Receives 8 Bytes of Data and
Stores in RAM Buffer
bq2024 Transmits
CRC of Previous Received 8 Bytes of Data
N
Code 5Ah
Y
Received
Contents of RAM buffer AND’ed with contents of
data memory offset by
address counter and stored in data
memory offset by address counter .
programming time required to be at
least t _EPROG when VPP Vdc on data pin
Voltage on Data ^N
Pin = VPP
Y
bq2024
Increments Address
Counter and Transmits 1
Byte of Data Memory
Indexed by Address Counter
bq2024
Transmits 1 Byte of Data Memory
at Address Counter
8th Byte
N
Transmitted
Y
NOTE: Individual bytes of address and data are transmitted LSB first
bq2024 Waits for Reset
(No Further Response)
Figure 9. WRITE MEMORY Command Flow
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