BQ2024 Datasheet, PDF (2/19 Pages) Texas Instruments – 1.5K-BIT SERIAL EPROM WITH SDQ INTERFACE

bq2024
SLUS770 – MAY 2007
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted⁽¹⁾
V_PU
I_OL
T_A
T_A(Comm)
T_stg
DC voltage applied to data
Low-level output current
ESD IEC 61000-4-2 Air discharge
Operating free-air temperature range
Communication free-air temperature range
Storage temperature range
Lead temperature (soldering, 10 s)
Data to V_SS, V_SS to data
Communication is specified by design
UNIT
–0.3 V to 7 V
40 mA
15 kV
–20°C to 70°C
–40°C to 85°C
–55°C to 125°C
260°C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
T_A = –20°C to 70°C; V_PU(min) = 2.65 V_DC to 5.5 V_DC, all voltages relative to VSS
PARAMETER
TEST CONDITION
I_DATA Supply current
V_OL Low-level output voltage
V_OH High-level output voltage
I_OL Low-level output current (sink)
V_IL Low-level input voltage
V_IH High-level input voltage
V_PP Programming voltage
V_PU = 5.5 V
Logic 0, V_PU = 5.5 V, I_OL = 4 mA, SDQ pin
Logic 0, V_PU = 2.65 V, I_OL = 2 mA
Logic 1
V_OL = 0.4 V, SDQ pin
Logic 0
Logic 1
MIN TYP MAX UNIT
20 µA
0.4
V
0.4
V_PU
5.5
4 mA
0.8 V
2.2
V
11.5
12 V
AC SWITCHING CHARACTERISTCS
T_A = –20°C to 70°C; V_PU(min) = 2.65 V_DC to 5.5 V_DC, all voltages relative to VSS
PARAMETER
TEST CONDITION
t_c
t_WSTRB
t_WDSU
t_WDH
Bit cycle time⁽¹⁾
Write start cycle⁽¹⁾
Write data setup⁽¹⁾
Write data hold⁽¹⁾⁽²⁾
t_rec
t_RSTRB
t_ODD
t_ODHO
t_RST
t_PPD
t_PP
t_EPROG
t_PSU
t_PREC
Recovery time⁽¹⁾
Read start cycle⁽¹⁾
Output data delay⁽¹⁾
Output data hold⁽¹⁾
Reset time⁽¹⁾
Presence pulse delay⁽¹⁾
Presence pulse⁽¹⁾
EPROM programming time
Program setup time
Program recovery time
For memory command only
(1) 5-kΩ series resistor between SDQ pin and V_PU. (See Figure 1)
(2) t_WDH must be less than t_c to account for recovery.
2
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MIN
60
1
t_WSTRB
60
1
5
1
t_RSTRB
17
480
15
60
2500
5
5
TYP MAX UNIT
120 µs
15 µs
15 µs
t_c µs
µs
13 µs
13 µs
60 µs
µs
60 µs
240 µs
µs
µs
µs