BQ2024 Datasheet, PDF (5/19 Pages) Texas Instruments – 1.5K-BIT SERIAL EPROM WITH SDQ INTERFACE

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bq2024
SDQI
Communications
Controller
SDQO
VSS
3
VPU
SDQ
1
VSS
2
HOST
bq2024
SLUS770 – MAY 2007
CPU
Figure 1. Typical Applications Circuit
Serial Communication
A host reads, programs, or checks the status of the bq2024 through the hierarchical command structure of the
SDQ interface. Figure 2 shows that the host must first issue a ROM command before the EPROM memory or
status can be read or modified. The ROM command either selects a specific device when multiple devices are
on the SDQ bus, or skips the selection process in single SDQ device applications.
Initialization
ROM Command Sequence
Memory/Status Command Sequence
Figure 2. General Command Sequence
Initialization
Initialization consists of two pulses, the RESET and the PRESENCE pulses. The host generates the RESET
pulse, while the bq2024 responds with the PRESENCE pulse. The host resets the bq2024 by driving the DATA
bus low for at least 480 µs. For more details, see the RESET section under SDQ Signaling.
ROM COMMANDS
READ ROM
The READ ROM command sequence is the fastest sequence that allows the host to read the 8-bit family code
and 48-bit identification number. It is used if only one SDQ slave device is attached to the bus. The READ ROM
sequence starts with the host generating the RESET pulse of at least 480 µs. The bq2024 responds with a
PRESENCE pulse. Next, the host continues by issuing the READ ROM command, 33h, and then reads the
ROM and CRC byte using the READ signaling (see the READ and WRITE signals section) during the data
frame.
Reset
and
Presence
Read ROM (33h)
Signals 1 1 0 0 1 1 0 ⁰
Family Code and Identification
Number (7 BYTES)
CRC (1 BYTE)
Figure 3. READ ROM Sequence
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