BQ2024 Datasheet, PDF (8/19 Pages) Texas Instruments – 1.5K-BIT SERIAL EPROM WITH SDQ INTERFACE

bq2024
SLUS770 – MAY 2007
www.ti.com
READ MEMORY/Field CRC
To read memory without CRC generation on 32-byte page boundaries, the ROM command is followed by the
READ MEMORY command, F0h, followed by the address low byte and then the address high byte.
NOTE:
As shown in Figure 8, individual bytes of address and data are transmitted LSB first.
An 8-bit CRC of the command byte and address bytes is computed by the bq2024 and read back by the host to
confirm that the correct command word and starting address were received. If the CRC read by the host is
incorrect, a reset pulse must be issued and the entire sequence must be repeated. If the CRC received by the
host is correct, the host issues read time slots and receives data from the bq2024 starting at the initial address
and continuing until the end of the 1536-bit data field is reached or until a reset pulse is issued. If reading occurs
through the end of memory space, the host may issue eight additional read time slots and the bq2024 responds
with an 8-bit CRC of all data bytes read from the initial starting byte through the last byte of memory. After the
CRC is received by the host, any subsequent read time slots appear as logical 1s until a reset pulse is issued.
Any reads ended by a reset pulse prior to reaching the end of memory does not have the 8-bit CRC available.
Initialization and ROM
Command
Sequence
READ MEMORY Command
F0h
Address Low
Byte
Read EPROM
Address High Read and Memory Until End
Byte
Verify CRC of EPROM
Memory
A0
A7 A8
A15
Figure 8. READ MEMORY/Field CRC
Read and
Verify CRC
WRITE MEMORY
The WRITE MEMORY command is used to program the 1536-bit EPROM memory field. The 1536-bit memory
field is programmed in 8-byte segments. Data is first written into an 8-byte RAM buffer one byte at a time. The
contents of the RAM buffer is then ANDed with the contents of the EPROM memory field when the programming
command is issued.
Figure 9 illustrates the sequence of events for programming the EPROM memory field. After issuing a ROM
command, the host issues the WRITE MEMORY command, 0Fh, followed by the low byte and then the high
byte of the starting address. The bq2024 calculates and transmits an 8-bit CRC based on the WRITE command
and address.
If at any time during the WRITE MEMORY process, the CRC read by the host is incorrect, a reset pulse must be
issued, and the entire sequence must be repeated.
After the bq2024 transmits the CRC, the host then transmits 8 bytes of data to the bq2024. Another 8-bit CRC is
calculated and transmitted based on the 8 bytes of data. If this CRC agrees with the CRC calculated by the host,
the host transmits the program command 5Ah and then applies the programming voltage for at least 2500 µs or
t_EPROG. The contents of the RAM buffer is then logically ANDed with the contents of the 8-byte EPROM offset by
the starting address.
The starting address can be any integer multiple of eight between 0000 and 00BF (hex) such as 0000, 0008,
and 0010 (hex).
The WRITE DATA MEMORY command sequence can be terminated at any point by issuing a reset pulse
except during the program pulse period t_PROG.
NOTE:
The bq2024 responds with the data from the selected EPROM address sent least
significant-bit first. This response should be checked to verify the programmed byte. If
the programmed byte is incorrect, then the host must reset the part and begin the
write sequence again.
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