BQ2024 Datasheet, PDF (14/19 Pages) Texas Instruments – 1.5K-BIT SERIAL EPROM WITH SDQ INTERFACE

bq2024
SLUS770 – MAY 2007
VPU _VIH
V _IL
Write ”1”
Write ”0”
t _WSTRB
t _WDSU
t _WDH
t _rec
Figure 14. Write Bit Timing Diagram
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READ
The READ bit timing diagram in Figure 15 shows that the host initiates the transmission of the bit by issuing the
t_RSTRB portion of the bit. The bq2024 then responds by either driving the DATA bus low to transmit a READ 0 or
releasing the DATA bus to transmit a READ 1.
VPU _{V IH}
V _IL
Read ”1”
Read ”0”
t _RSTRB
t _ODD
t _ODHO
t _REC
Figure 15. Read Bit Timing Diagram
PROGRAM PULSE
V_PP
V_PU
V_SS
t_PSU
t_PRE
t_EPROG
t_PFE
t_PREC
Figure 16. Program Pulse Timing Diagram
IDLE
If the bus is high, the bus is in the IDLE state. Bus transactions can be suspended by leaving the DATA bus in
IDLE. Bus transactions can resume at any time from the IDLE state.
CRC Generation
The bq2024 has an 8-bit CRC stored in the most significant byte of the 64-bit ROM. The bus master can
compute a CRC value from the first 56 bits of the 64-bit ROM and compare it to the value stored within the
bq2024 to determine if the ROM data has been received error-free by the bus master. The equivalent polynomial
function of this CRC is: X⁸ + X⁵ + X⁴ +1.
Under certain conditions, the bq2024 also generates an 8-bit CRC value using the same polynomial function just
shown and provides this value to the bus master to validate the transfer of command, address, and data bytes
from the bus master to the bq2024. The bq2024 computes an 8-bit CRC for the command, address, and data
bytes received for the WRITE MEMORY and the WRITE STATUS commands and then outputs this value to the
bus master to confirm proper transfer. Similarly, the bq2024 computes an 8-bit CRC for the command and
address bytes received from the bus master for the READ MEMORY, READ STATUS, and READ DATA/
GENERATE 8-BIT CRC commands to confirm that these bytes have been received correctly. The CRC
generator on the bq2024 is also used to provide verification of error-free data transfer as each page of data from
the 1536-bit EPROM is sent to the bus master during a READ DATA/GENERATE 8-BIT CRC command, and for
the eight bytes of information in the status memory field.
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