BQ2024 Datasheet, PDF (7/19 Pages) Texas Instruments – 1.5K-BIT SERIAL EPROM WITH SDQ INTERFACE

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bq2024
SLUS770 – MAY 2007
SKIP ROM
This SKIP ROM command, CCh, allows the host to access the memory/status functions without issuing the
64-bit ROM code sequence. The SKIP ROM command is directly followed by a memory/status functions
command. Because this command can cause bus collisions when multiple SDQ devices are on the same bus,
this command should be issued in single device applications.
Reset
and
Skip ROM (CCh)
Presence
0
1
0
1
0
1
0
1
Signals
Figure 6. SKIP ROM Sequence
MEMORY/STATUS FUNCTION COMMANDS
Six memory/status function commands allow read and modification of the 1536-bit EPROM data memory or the
64-bit EPROM status memory. There are two types of READ MEMORY command, plus the WRITE MEMORY,
READ STATUS, and WRITE STATUS commands. Additionally, the part responds to a PROGRAM PROFILE
byte command. The bq2024 responds to memory/status function commands only after a part is selected by a
ROM command.
READ DATA MEMORY COMMANDS
Two READ MEMORY commands are available on the bq2024. Both commands are used to read data from the
1536-bit EPROM data field. They are the READ MEMORY/Page CRC and the READ MEMORY/Field CRC
commands. The READ MEMORY/Page CRC generates CRC at the end any 32-byte page boundary whereas
the READ MEMORY/Field CRC generates CRC when the end of the 1536-bit data memory is reached.
READ MEMORY/Page CRC
To read memory and generate the CRC at the 32-byte page boundaries of the bq2024, the ROM command is
followed by the READ MEMORY/Generate CRC command, C3h, followed by the address low byte and then the
address high byte.
An 8-bit CRC of the command byte and address bytes is computed by the bq2024 and read back by the host to
confirm that the correct command word and starting address were received. If the CRC read by the host is
incorrect, a reset pulse must be issued and the entire sequence must be repeated. If the CRC received by the
host is correct, the host issues read time slots and receives data from the bq2024 starting at the initial address
and continuing until the end of a 32-byte page is reached. At that point, the host sends eight additional read time
slots and receive an 8-bit CRC that is the result of shifting into the CRC generator all of the data bytes from the
initial starting byte to the last byte of the current page. Once the 8-bit CRC has been received, data is again
read from the 1536-bit EPROM data field starting at the next page. This sequence continues until the final page
and its accompanying CRC are read by the host. Thus each page of data can be considered to be 33 bytes
long, the 32 bytes of user-programmed EPROM data and an 8-bit CRC that gets generated automatically at the
end of each page.
Initialization and ROM
Command Sequence
READ
MEMORY/Generate
CRC Command
Address Low Byte Address High Byte
C3h
A0
A7 A8
A15
Read and
Verify CRC
NOTE: Individual bytes of address and data are transmitted LSB first.
Figure 7. READ MEMORY/Page CRC
EPROM Memory and CRC
Byte
Generated at 32-Byte
Page
Boundaries
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