TLK4015 Datasheet, PDF (8/24 Pages) Texas Instruments – QUAD 0.6 TO 1.5 Gbps TRANSCEIVER

TLK4015
QUAD 0.6 to 1.5 Gbps TRANSCEIVER
SLLS541 – DECEMBER 2002
detailed description (detailed descriptions are applicable to each of the four separate channels)
transmit interface
The transmitter portion registers valid incoming 16-bit-wide data (TDx[0–15]) on the rising edge of the
GTx_CLK. The data is then 8-bit/10-bit encoded, serialized, and transmitted sequentially over the differential
high-speed I/O channel. The clock multiplier multiplies the reference clock (GTx_CLK) by a factor of 10, creating
a bit clock. This internal bit clock is fed to the parallel-to-serial shift register, which transmits data on both the
rising and falling edges of the bit clock, providing a serial data rate that is 20 times the reference clock. Data
is transmitted LSB (TDx0) first. The transmitter also inserts commas at the beginning of the transmission for
byte synchronization.
transmit data bus
The transmit bus interface accepts 16-bit wide single-ended TTL parallel data at the TDx[0–15] terminals. Data
is valid on the rising edge of the GTx_CLK when the Tx_EN is asserted high and the Tx_ER is deasserted low.
The GTx_CLK is used as the word clock. The data, enable, and clock signals must be properly aligned as shown
in Figure 1 . Detailed timing information can be found in the electrical characteristics table.
GTx_CLK
TDxn, Tx_EN, Tx_ER
tsu
th
Figure 1. Transmit Timing Waveform
transmittion latency
The data transmission latency of the TLK4015 is defined as the delay from the initial 16-bit word load to the serial
transmission of bit 0. The transmit latency is fixed once the link is established. However, due to silicon process
variations and implementation variables such as supply voltage and temperature, the exact delay varies slightly.
The minimum transmit latency (T latency ) is 34 bit times; the maximum is 38 bit times. Figure 2 illustrates the
timing relationship between the transmit data bus, the GTx_CLK, and the serial transmit terminals.
Transmitted 20-Bit Word
DOUTTxP,
DOUTTxN
TDx[0–15]
td(Tlxatency)
16-Bit Word to Transmit
GTx_CLK
Figure 2. Transmit Latency
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