TLK4015 Datasheet, PDF (7/24 Pages) Texas Instruments – QUAD 0.6 TO 1.5 Gbps TRANSCEIVER

TLK4015
QUAD 0.6 to 1.5 Gbps TRANSCEIVER
SLLS541 – DECEMBER 2002
Terminal Functions (Continued)
NAME
RREFA
RREFB
RREFC
RREFD
TA_EN
TB_EN
TC_EN
TD_EN
TERMINAL
NUMBER
A5
E17
N17
U5
J2
B9
N12
M5
TA_ER
J4
TB_ER
D9
TC_ER
M10
TD_ER
K6
TDA[0–15]
TDB[0–15]
TDC[0–15]
TDD[0–15]
TESTENA
TESTENB
TESTENC
TESTEND
VDD
VDDAA
VDDAB
VDDAC
VDDAD
† _{Hi-Z on power up}
‡ _{Internal 10-kΩ pullup}
§ _{Internal 10-kΩ pulldown}
¶ _{Low on power up}
A2, A1, B2, C2,
B1, C1, D2, D1,
E1, F1, F2, G1,
H1, G2, J1, H3
B17, A17, B16, B15,
A16, A15, B14, A14,
A13, A12, B12, A11,
A10, B11, A9, C10
K17, K16, M15, P14,
N14, K14, L14, M14,
K12, L13, M13, N13,
L12, M12, P13, M11
U8, T8, R6, P4,P5,
R8, P7, P6,M8,
N7,N6, N5,M7, M6,
N4, L6
H6
F10
P11
M3
C8, C12, C14, D3,
D11, F3, F9,G4,
H15, J12, J13, J16,
K15, L5, N3, N8,
N11, P15, R4, R13,
U9
B5, C5,
E15, E16,
N15, N16,
R5, T5
TYPE
DESCRIPTION
I Reference resistor, channels A–D. The RREFx terminal is used to connect to an
external reference resistor. The other side of the resistor is connected to VDDA .
The resistor is used to provide an accurate current reference to the transmitter and
receiver I/O circuitry.
I^§ Transmit enable (with pulldown), channels A–D. Tx_EN in combination with Tx_ER
indicates the protocol device is presenting data on the transmit data bus for
transmission. Tx_EN must be asserted high with the first word of the preamble and
remain asserted while all words to be transmitted are presented on the transmit data
bus(TDx). Tx_EN must be negated prior to the first rising edge of GTx_CLK
following the final word of a frame.
I^§ Transmit error coding (with pulldown), channels A–D. When Tx_ER and Tx_EN are
high, indicates that the transceiver generates an error somewhere in the frame
presently being transferred. When Tx_ER is asserted high and Tx_EN is
deasserted low, indicates the protocol device is presenting carrier extension data.
When Tx_ER is deasserted low with Tx_EN asserted high, indicates that normal
data is being presented.
I Transmit data bus, channels A–D. These inputs carry the 16-bit parallel data output
from a protocol device to the transceiver for encoding, serialization, and
transmission. This 16-bit parallel data is clocked into the transceiver on the rising
edge of GTx_CLK as shown in Figure 9.
I
I
I
I^§ Test mode enable (with pulldown), channels A–D. This terminal should be left
unconnected or tied low.
Digital logic power. Provides power for all digital circuitry and digital I/O buffers.
Analog power, channels A–D. VDDAx provides a supply reference for the
high-speed analog circuits, receiver and transmitter.
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