TLK4015 Datasheet, PDF (10/24 Pages) Texas Instruments – QUAD 0.6 TO 1.5 Gbps TRANSCEIVER

TLK4015
QUAD 0.6 to 1.5 Gbps TRANSCEIVER
SLLS541 – DECEMBER 2002
detailed description (continued)
high-speed data output
The high-speed data output driver consists of a current-mode logic (CML) differential pair that can be optimized
for a particular transmission line impedance and length. The line can be directly coupled or ac-coupled. Refer
to Figure 14 and Figure 15 for termination details.
receive interface
The receiver portion of the TLK4015 accepts 8-bit/10-bit encoded differential serial data. The interpolator and
clock recovery circuit lock to the data stream and extract the bit rate clock. This recovered clock is used to retime
the input data stream. The serial data is then aligned to two separate 10-bit word boundaries, 8-bit/10-bit
decoded and output on a 16-bit wide parallel bus synchronized to the extracted receive clock.
receive data bus
The receive bus interface drives 16-bit wide single-ended TTL parallel data at the RDx[0–15] terminals. Data
is valid on the rising edge of the Rx_CLK when the Rx_DV/LOSx is asserted high and the Rx_ER is deasserted
low. The Rx_CLK is used as the recovered word clock. The data, enable, and clock signals are aligned as shown
in Figure 3. Detailed timing information can be found in the switching characteristics table.
Rx_CLK
RDxn, Rx_DV, Rx_ER
tsu
th
Figure 3. Receive Timing Waveform
data reception latency
The serial-to-parallel data receive latency is the time from when the first bit arrives at the receiver until it is output
as the aligned parallel word with RDx0 received as the first bit. The receive latency is fixed once the link is
established. However, due to silicon process variations and implementation variables such as supply voltage
and temperature, the exact delay varies slightly. The minimum receive latency (R latency ) is 76 bit times; the
maximum is 107 bit times. Figure 4 illustrates the timing relationship between the serial receive terminals, the
recovered word clock (Rx_CLK), and the receive data bus.
20-Bit Encoded Word
DINRxP,
DINRxN
RDx[0–15]
td(Rlxatency)
16-Bit Decoded Word
Rx_CLK
Figure 4. Receive Latency
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