TLK4015 Datasheet, PDF (5/24 Pages) Texas Instruments – QUAD 0.6 TO 1.5 Gbps TRANSCEIVER

TLK4015
QUAD 0.6 to 1.5 Gbps TRANSCEIVER
SLLS541 – DECEMBER 2002
Terminal Functions
TERMINAL
NAME
NUMBER
DINRAP, DINRAN
DINRBP, DINRBN
DINRCP, DINRCN
DINRDP, DINRDN
A6, A7
F17, G17
P17, R17
U4, U3
DOUTTAP, DOUTTAN
DOUTTBP, DOUTTBN
DOUTTCP, DOUTTCN
DOUTTDP, DOUTTDN
A3, A4
C17, D17
L17, M17
U7, U6
ENABLEA
ENABLEB
ENABLEC
ENABLED
GND
GNDA
GTA_CLK
GTB_CLK
GTC_CLK
GTD_CLK
LCKREFNA
LCKREFNB
LCKREFNC
LCKREFND
H5
E10
M9
J6
B10, C3, C7, C9,
C11, C13, C15, E3,
E9, G3, G7, G8,
G9, G10, G11, G15,
H2, H7, H8, H9,
H10, H11, J5, J7,
J8, J9, J10, J11,
J14, J15, J17, K7,
K8, K9, K10, K11,
L3, L7, L8, L9,
L10, L11, L15, P3,
P9, R3, R7, R11,
R12, R14, R15, T10
B3, B4, B6, B7,
C16, D16, F16,G16,
L16, M16,P16, R16,
T3, T4, T6, T7
E2
B13
K13
P8
F4
D12
N10
K5
† _{Hi-Z on power up}
‡ _{Internal 10 kΩ pullup}
§ _{Internal 10 kΩ pulldown}
TYPE
DESCRIPTION
I Serial receive inputs, channels A–D. DINRxP and DINRxN together are the
differential serial input interface from a copper or an optical I/F module.
O^† Serial transmit outputs (Hi-Z on power up), channels A–D. DOUTTxP and
DOUTTxN are differential serial outputs that interface to copper or an optical I/F
module. These terminals transmit NRZ data at a rate of 20 times the GTx_CLK
value. DOUTTxP and DOUTTxN are put in a high-impedance state when
LOOPENx is high and are active when LOOPENx is low. During power-on reset
these terminals are high-impedance.
I^‡ Device enable (with pullup), channels A–D. When this terminal is held low, the
device is placed in power-down mode. Only the signal detect circuit on the serial
receive pair is active. When asserted high while the device is in power-down mode,
the transceiver goes into power-on reset before beginning normal operation.
Digital logic ground. Provides a ground for the logic circuits and digital I/O buffers.
Analog ground. GNDA provides a ground reference for the high-speed analog
circuits, RX and TX.
I Reference clock, channels A–D. GTx_CLK is a continuous external input clock that
synchronizes the transmitter interface signals Tx_EN, Tx_ER and TDx. The
frequency range of the GTx_CLK is 30 MHz to 75 MHz. The transmitter uses the
rising edge of this clock to register the 16-bit input data (TDx) for serialization.
I^‡ Lock to reference (with pullup), channels A–D. When LCKREFNx is low, the
receiver clock is frequency locked to GTx_CLK. This places the device in a
transmit-only mode because the receiver is not tracking the data. When
LCKREFNx is deasserted low, the receive data bus terminals, RDx[0–15], Rx_CLK
and Rx_ER, Rx_DV/LOSx are in a high-impedance state.
When LCKREFNx is asserted high, the receiver is locked to the received data
stream and must receive valid codes from the synchronization state machine
before the transmitter is enabled.
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