TLK4015 Datasheet, PDF (16/24 Pages) Texas Instruments – QUAD 0.6 TO 1.5 Gbps TRANSCEIVER

TLK4015
QUAD 0.6 to 1.5 Gbps TRANSCEIVER
SLLS541 – DECEMBER 2002
reference clock (GTx_CLK) timing requirements over recommended operating conditions (unless
otherwise noted)
PARAMETER
Frequency
Frequency
Frequency tolerance
Duty cycle
Jitter
TEST CONDITIONS
Minimum data rate
Maximum data rate
Peak-to-peak
MIN
Typ–0.01%
Typ–0.01%
–100
40%
TYP MAX
30 Typ+0.01%
75 Typ+0.01%
100
50%
60%
40
UNIT
MHz
MHz
ppm
ps
TTL input electrical characteristics over recommended operating conditions (unless otherwise
noted), TTL signals: TDx0–TDx15, GTx_CLK, LOOPENx, LCKREFNx, PRBSENx
PARAMETER
VIH
High-level input voltage
VIL
Low-level input voltage
IIH
Input high current
IIL
Input low current
CI
tr
GTx_CLK, Tx_EN, Tx_ER, TDx Rise time
tf
GTx_CLK, Tx_EN, Tx_ER, TDx Fall time
tsu
TDx, Tx_EN, Tx_ER setup to ↑ GTx_CLK
th
TDx, Tx_EN, Tx_ER hold to ↑ GTx_CLK
TEST CONDITIONS
See Figure 9
See Figure 9
VDD = MAX,
VDD = MAX,
0.8V to 2 V
VIN = 2 V
VIN = 0.4 V
0.8 V to 2.0 V, C = 5 pF, See Figure 9
2.0 V to 0.8 V, C = 5 pF, See Figure 9
See Figure 9
See Figure 9
MIN TYP MAX UNIT
2
3.6 V
0.80 V
40 µA
–40
µA
4 pF
1
ns
1
ns
1.5
ns
0.4
ns
GTx_CLK
Tx_ER, Tx_EN,
TDx[0–15]
tr
tsu
tf
th
Figure 9. TTL Data-Input-Valid Levels for AC Measurements
tf
tr
3.6 V
2V
0.8 V
0V
3.6 V
2V
0.8 V
0V
16
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