TLK4015 Datasheet, PDF (12/24 Pages) Texas Instruments – QUAD 0.6 TO 1.5 Gbps TRANSCEIVER

TLK4015
QUAD 0.6 to 1.5 Gbps TRANSCEIVER
SLLS541 – DECEMBER 2002
detailed description (continued)
loss of signal detection
The TLK4015 has a loss-of-signal detection circuit for conditions where the incoming signal no longer has a
sufficient voltage level to keep the clock recovery circuit in lock. The signal detection circuit is an indication of
gross signal error conditions, such as a detached cable or no signal being transmitted, and not an indication
of signal coding health. The TLK4015 reports this condition by asserting the Rx_DV/LOSx, Rx_ER and
RDx[0–15] all to a high state. As long as the signal is above 200 mV in differential magnitude, the LOS circuit
does not signal an error condition.
synchronization and initialization
The TLK4015 has a synchronization state machine which is responsible for handling link initialization and
synchronization. Upon power up or reset, the state machine enters the acquisition (ACQ) state and searches
for IDLE. Upon receiving three consecutive IDLEs or carrier extends, the state machine enters the
synchronization (SYNC) state. If, during the acquisition process, the state machine receives valid data or an
error propagation code, it immediately transitions to the SYNC state. The SYNC state is the state for normal
device transmission and reception. The initialization and synchronization state diagram is provided in Figure 5.
Invalid Code
Word Received
Power-Up/Reset
3 Invalid Code
Words Received
ACQ
(Link Acquisition)
3 Consecutive Valid IDLEs or Carrier Extends,
or
1 Valid Data or Error Propagation
Loss of Link
Link Established
Valid Code
Word Received
CHECK
(Look for Valid Code)
1 Invalid Code
Word Received
Link in Question
SYNC
(Normal Operation)
Link Re-established
4 Consecutive Valid Code Words Received
Figure 5. Initialization and Synchronization State Diagram
If during normal transmission and reception, an invalid code is received, the TLK4015 notifies the attached
system or protocol device as described in the comma detect and 8-bit/10-bit decoding section. The
synchronization state machine transitions to the CHECK state. The CHECK state determines whether the
invalid code received was caused by a spurious event or a loss of the link. If, in the CHECK state, the decoder
sees four consecutive valid codes, the state machine determines the link is good and transitions back to the
SYNC state for normal operation. If, in the CHECK state, the decoder sees three invalid codes (not required
to be consecutive), the TLK4015 determines a loss of the link has occurred and transitions the
synchronization-state machine back to the link-acquisition state (ACQ).
The state of the transmit data bus, control terminals, and serial outputs during the link acquisition process is
illustrated in Figure 6.
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