TLK2711-SP Datasheet, PDF (8/21 Pages) Texas Instruments – 1.6-Gbps to 2.5-Gbps Class V Transceiver

TLK2711-SP
SGLS307D – JULY 2006 – REVISED JULY 2009 .............................................................................................................................................................. www.ti.com
RXCLK
RXD0−RXD15
t_su
t_h
RKLSB, RKMSB
Figure 5. Receive Timing Waveform
Data Reception Latency
The serial-to-parallel data receive latency is the time from when the first bit arrives at the receiver until it is output
in the aligned parallel word. The receive latency is fixed once the link is established. However, due to silicon
process variations and implementation variables such as supply voltage and temperature, the exact delay varies
slightly. The minimum receive latency t_{d(Rx latency)} is 76 bit times; the maximum is 107 bit times. Figure 6 shows
the timing relationship between the serial receive terminals, the recovered word clock (RXCLK), and the receive
data bus.
20-Bit Encoded Word
RXN,
RXP
RXD0−RXD15
t_{d(Rx latency)}
16-Bit Decoded Word
RXCLK
Figure 6. Receiver Latency
Serial to Parallel
Serial data is received on the RXP and RXN terminals. The interpolator and clock recovery circuit locks to the
data stream if the clock to be recovered is within 200 PPM of the internally generated bit rate clock. The
recovered clock is used to retime the input data stream. The serial data is then clocked into the serial-to-parallel
shift registers. The 10-bit-wide parallel data is then multiplexed and fed into two separate 8-bit/10-bit decoders,
where the data is then synchronized to the incoming data stream word boundary by detection of the comma
8-bit/10-bit synchronization pattern.
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